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| author | Atish Patra <atishp@rivosinc.com> | 2022-07-22 09:50:44 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-11 14:36:06 -0700 |
| commit | bf952a290f7a9d818204b9b68e861655f8b15a65 (patch) | |
| tree | 2dd0eade51f4649e78175fed24a8283d385fe224 /drivers/clocksource/timer-riscv.c | |
| parent | f2906aa863381afb0015a9eb7fefad885d4e5a56 (diff) | |
| download | linux-bf952a290f7a9d818204b9b68e861655f8b15a65.tar.gz linux-bf952a290f7a9d818204b9b68e861655f8b15a65.tar.bz2 linux-bf952a290f7a9d818204b9b68e861655f8b15a65.zip | |
RISC-V: Add SSTC extension CSR details
This patch just introduces the required CSR fields related to the
SSTC extension.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220722165047.519994-2-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'drivers/clocksource/timer-riscv.c')
0 files changed, 0 insertions, 0 deletions