| Age | Commit message (Expand) | Author |
|---|
| 2017-03-20 | clk: tegra: Add CEC clock | Peter De Schrijver |
| 2016-08-24 | clk: tegra: remove TEGRA_PLL_USE_LOCK for PLLD/PLLD2 | Vince Hsu |
| 2016-06-30 | clk: tegra: Initialize UTMI PLL when enabling PLLU | Andrew Bresticker |
| 2016-04-28 | clk: tegra: Special-case mipi-cal parent on Tegra114 | Thierry Reding |
| 2016-03-02 | clk: tegra: Remove CLK_IS_ROOT | Stephen Boyd |
| 2015-11-20 | clk: tegra: pll: Update PLLM handling | Danny Huang |
| 2015-11-20 | clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate | Rhyland Klein |
| 2015-11-20 | clk: tegra: pll: Don't unconditionally set LOCK flags | Rhyland Klein |
| 2015-11-20 | clk: tegra: Constify pdiv-to-hw mappings | Thierry Reding |
| 2015-11-18 | clk: tegra: Format tables consistently | Thierry Reding |
| 2015-11-18 | clk: tegra: Miscellaneous coding style cleanups | Thierry Reding |
| 2015-11-18 | clk: tegra: Fix 26 MHz oscillator frequency | Thierry Reding |
| 2015-10-20 | clk: tegra: Modify tegra_audio_clk_init to accept more plls | Rhyland Klein |
| 2015-07-20 | clk: tegra: Properly include clk.h | Stephen Boyd |
| 2015-04-10 | clk: tegra: Use generic tegra_osc_clk_init() on Tegra114 | Thierry Reding |
| 2015-04-10 | clk: tegra: Various whitespace cleanups | Thierry Reding |
| 2015-02-02 | clk: tegra: Define PLLD_DSI and remove dsia(b)_mux | Mark Zhang |
| 2014-11-26 | clk: tegra: Implement memory-controller clock | Thierry Reding |
| 2014-06-25 | clk: tegra: fix vi_sensor clocks on Tegra124 | Peter De Schrijver |
| 2014-05-22 | clk: tegra: Initialize xusb clocks | Andrew Bresticker |
| 2014-05-22 | clk: tegra: Fix xusb_hs_src clock hierarchy | Andrew Bresticker |
| 2014-02-17 | clk: tegra: fix sdmmc clks on Tegra1x4 | Andrew Bresticker |
| 2013-12-11 | clk: tegra: implement a reset driver | Stephen Warren |
| 2013-11-26 | clk: tegra: Initialize DSI low-power clocks | Thierry Reding |
| 2013-11-26 | clk: tegra: add FUSE clock device | Alexandre Courbot |
| 2013-11-26 | clk: tegra114: Initialize clocks needed for HDMI | Mikko Perttunen |
| 2013-11-26 | clk: tegra: introduce common gen4 super clock | Peter De Schrijver |
| 2013-11-26 | clk: tegra: move PMC, fixed clocks to common files | Peter De Schrijver |
| 2013-11-26 | clk: tegra: move periph clocks to common file | Peter De Schrijver |
| 2013-11-26 | clk: tegra: move audio clk to common file | Peter De Schrijver |
| 2013-11-26 | clk: tegra: add clkdev registration infra | Peter De Schrijver |
| 2013-11-26 | clk: tegra: move fields to tegra_clk_pll_params | Peter De Schrijver |
| 2013-11-26 | clk: tegra: use pll_ref as the pll_e parent | Peter De Schrijver |
| 2013-11-26 | clk: tegra: move some PLLC and PLLXC init to clk-pll.c | Peter De Schrijver |
| 2013-11-26 | clk: tegra: common periph_clk_enb_refcnt and clks | Peter De Schrijver |
| 2013-11-26 | clk: tegra: simplify periph clock data | Peter De Schrijver |
| 2013-11-26 | clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3d | Thierry Reding |
| 2013-11-26 | clk: tegra: Set the clk parent of host1x to pll_p | Andrew Chew |
| 2013-11-26 | clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks | Peter De Schrijver |
| 2013-11-25 | clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2 | Mark Zhang |
| 2013-11-25 | clk: tegra: Fix vde/2d/3d clock src offset | Mark Zhang |
| 2013-11-25 | clk: tegra: Correct sbc mux width & parent | Mark Zhang |
| 2013-11-25 | clk: tegra: replace enum tegra114_clk by binding header | Peter De Schrijver |
| 2013-09-09 | Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux | Linus Torvalds |
| 2013-08-19 | clk: add CLK_SET_RATE_NO_REPARENT flag | James Hogan |
| 2013-08-12 | clk: tegra114: add LP1 suspend/resume support | Joseph Lo |
| 2013-08-08 | clk: tegra114: Fix incorrect placement of __initdata | Sachin Kamat |
| 2013-07-19 | clk: tegra: add suspend/resume function for tegra_cpu_car_ops | Joseph Lo |
| 2013-07-03 | Merge tag 'clk-for-linus-3.11' of git://git.linaro.org/people/mturquette/linux | Linus Torvalds |
| 2013-06-18 | clk: tegra: T114: add DFLL DVCO reset control | Paul Walmsley |
