| Age | Commit message (Expand) | Author |
|---|
| 2019-09-06 | x86/cpu: Update init data for new Airmont CPU model | Rahul Tanwar |
| 2019-05-09 | x86/apic: Rename 'lapic_timer_frequency' to 'lapic_timer_period' | Daniel Drake |
| 2018-10-02 | x86/cpu: Sanitize FAM6_ATOM naming | Peter Zijlstra |
| 2018-07-03 | x86/platform/intel-mid: Remove custom TSC calibration | Andy Shevchenko |
| 2018-07-03 | x86/tsc: Use SPDX identifier and update Intel copyright | Andy Shevchenko |
| 2018-07-03 | x86/tsc: Convert to use x86_match_cpu() and INTEL_CPU_FAM6() | Andy Shevchenko |
| 2018-07-03 | x86/tsc: Add missing header to tsc_msr.c | Andy Shevchenko |
| 2016-11-18 | x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Atom SoCs | Bin Gao |
| 2016-07-11 | x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration | Len Brown |
| 2016-07-10 | x86/tsc_msr: Add Airmont reference clock values | Len Brown |
| 2016-07-10 | x86/tsc_msr: Correct Silvermont reference clock values | Len Brown |
| 2016-07-10 | x86/tsc_msr: Update comments, expand definitions | Len Brown |
| 2016-07-10 | x86/tsc_msr: Remove debugging messages | Len Brown |
| 2016-07-10 | x86/tsc_msr: Identify Intel-specific code | Len Brown |
| 2016-07-10 | Revert "x86/tsc: Add missing Cherrytrail frequency to the table" | Len Brown |
| 2016-05-12 | x86/tsc: Add missing Cherrytrail frequency to the table | Jeremy Compostella |
| 2016-05-06 | x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO | Chen Yu |
| 2014-02-19 | x86: tsc: Add missing Baytrail frequency to the table | Mika Westerberg |
| 2014-02-19 | x86, tsc: Fallback to normal calibration if fast MSR calibration fails | Thomas Gleixner |
| 2014-01-16 | x86, tsc, apic: Unbreak static (MSR) calibration when CONFIG_X86_LOCAL_APIC=n | H. Peter Anvin |
| 2014-01-15 | x86, tsc: Add static (MSR) TSC calibration on Intel Atom SoCs | Bin Gao |
