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2024-06-23arm64: dts: hisilicon: hi3660: add dedicated hi3660-usb3-otg-bc compatibleKrzysztof Kozlowski
Each syscon node must come with a dedicated/specific compatible, which is also reported by dtbs_check: hi3660-hikey960.dtb: usb3_otg_bc@ff200000: compatible: ['syscon', 'simple-mfd'] is too short Link: https://lore.kernel.org/r/20240518204443.122586-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-29Merge tag 'dt64-cleanup-6.10' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt Minor improvements in ARM64 DTS for v6.10 Fixes, which might have practical impact, however things were broken for long enough to justify pushing it regular path: 1. ARM Juno: shorten node names for thermal zones, because Linux drivers have strict limit of 20 characters. 2. HiSilicon: correct size of GIC GICC address space and add missing GICH and GICV spaces, add cache info to properly describe cache topology and solve kernel boot warning. Several cleanups: 1. Use capital "OR" for multiple licenses in SPDX. 2. Correct white-spaces for code readability. 3. Fix W=1 dtc compiler warnings, which should not have practical impact for Amazon, APM, Cavium, Realtek, Socionext Uniphier and Spreadtrum like: - missing unit addresses, - nodes not belonging to soc node, - not using generic node names, - few incorrect unit addresses. * tag 'dt64-cleanup-6.10' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt: (28 commits) arm64: dts: cavium: thunder2-99xx: drop redundant reg-names arm64: dts: amazon: alpine-v3: correct gic unit addresses arm64: dts: amazon: alpine-v3: drop cache nodes unit addresses arm64: dts: amazon: alpine-v3: add missing io-fabric unit addresses arm64: dts: amazon: alpine-v2: move non-MMIO node out of soc arm64: dts: amazon: alpine-v2: add missing io-fabric unit addresses arm64: dts: apm: shadowcat: move non-MMIO node out of soc arm64: dts: apm: storm: move non-MMIO node out of soc arm64: dts: cavium: correct unit addresses arm64: dts: cavium: move non-MMIO node out of soc arm64: dts: realtek: rtc16xx: add missing unit address to soc node arm64: dts: realtek: rtd139x: add missing unit address to soc node arm64: dts: realtek: rtd129x: add missing unit address to soc node arm64: dts: uniphier: ld20-global: drop audio codec port unit address arm64: dts: uniphier: ld20-global: use generic node name for audio-codec arm64: dts: uniphier: ld11-global: drop audio codec port unit address arm64: dts: uniphier: ld11-global: use generic node name for audio-codec arm64: dts: sharkl3: add missing unit addresses arm64: dts: whale2: add missing ap-apb unit address arm64: dts: sc9860: move GIC to soc node ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-04-19arm64: dts: hisilicon: hi6220: correct tsensor unit addressesKrzysztof Kozlowski
Correct unit address to fix dtc W=1 warnings: hi6220.dtsi:855.31-862.5: Warning (simple_bus_reg): /soc/tsensor@0,f7030700: simple-bus unit address format error, expected "f7030700" Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-19arm64: dts: hisilicon: hi6220-hikey: drop unit addresses from fixed regulatorsKrzysztof Kozlowski
Fixed regulators are not part of any MMIO bus, so they should not have unit addresses. This fixes dtc W=1 warnings: hi6220-hikey.dts:85.26-92.4: Warning (unit_address_vs_reg): /regulator@0: node has a unit name, but no reg or ranges property hi6220-hikey.dts:94.27-102.4: Warning (unit_address_vs_reg): /regulator@1: node has a unit name, but no reg or ranges property hi6220-hikey.dts:104.26-113.4: Warning (unit_address_vs_reg): /regulator@2: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-19arm64: dts: hisilicon: hi6220-hikey: add missing port@0 regKrzysztof Kozlowski
adv7533 ports should have "reg" propeties, as reported by dtc W=1 warnings: hi6220-hikey.dts:516.11-520.6: Warning (unit_address_vs_reg): /soc/i2c@f7102000/adv7533@39/ports/port@0: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-19arm64: dts: hisilicon: hip07: correct unit addressesKrzysztof Kozlowski
Correct several nodes' unit addresses to fix dtc W=1 warnings: arch/arm64/boot/dts/hisilicon/hip07.dtsi:1382.23-1520.5: Warning (simple_bus_reg): /soc/dsa@c7000000: simple-bus unit address format error, expected "c5000000" arch/arm64/boot/dts/hisilicon/hip07.dtsi:1727.29-1747.5: Warning (simple_bus_reg): /soc/pcie@a00a0000: simple-bus unit address format error, expected "af800000" arch/arm64/boot/dts/hisilicon/hip07.dtsi:1748.29-1788.5: Warning (simple_bus_reg): /soc/crypto@d2000000: simple-bus unit address format error, expected "d0000000" Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-19arm64: dts: hisilicon: hip07: move non-MMIO node out of socKrzysztof Kozlowski
Non-MMIO devices, which are BTW not really part of the SoC, should not be within simple-bus, as reported by dtc W=1 warning: hip07.dtsi:1486.20-1493.5: Warning (unit_address_vs_reg): /soc/ethernet@4: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-13arm64: dts: hisilicon: hip06: correct unit addressesKrzysztof Kozlowski
Correct dsa and pcie unit addresses to fix dtc W=1 warnings: hip06.dtsi:439.23-571.5: Warning (simple_bus_reg): /soc/dsa@c7000000: simple-bus unit address format error, expected "c5000000" Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-13arm64: dts: hisilicon: hip06: move non-MMIO node out of socKrzysztof Kozlowski
Non-MMIO devices, which are BTW not really part of the SoC, should not be within simple-bus, as reported by dtc W=1 warning: hip06.dtsi:377.18-381.5: Warning (simple_bus_reg): /soc/refclk: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-13arm64: dts: hisilicon: hip05-d02: correct local-bus unit addressesKrzysztof Kozlowski
Correct local-bus children unit addresses to fix dtc W=1 warnings: hip05-d02.dts:57.16-76.4: Warning (simple_bus_reg): /soc/local-bus@80380000/nor-flash@0,0: simple-bus unit address format error, expected "0" hip05-d02.dts:78.11-81.4: Warning (simple_bus_reg): /soc/local-bus@80380000/cpld@1,0: simple-bus unit address format error, expected "100000000" Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-13arm64: dts: hisilicon: hip05: move non-MMIO node out of socKrzysztof Kozlowski
Non-MMIO devices, which are BTW not really part of the SoC, should not be within simple-bus, as reported by dtc W=1 warning: hip05.dtsi:301.30-305.5: Warning (simple_bus_reg): /soc/refclk200mhz: missing or empty reg/ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2024-04-08arm64: dts: hi3798cv200: add cache infoYang Xiwen
During boot, the kernel complains: [ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0 So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1 i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache) With this patch, the line above is gone and the following info is added to the output of `lscpu`: Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) L2: 512 KiB (1 instance) Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Link: https://lore.kernel.org/r/20240219-cache-v3-3-a33c57534ae9@outlook.com [krzysztof: drop Fixes/cc-stable, because this is a missing feature, not a fix] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-08arm64: dts: hi3798cv200: add GICH, GICV register space and irqYang Xiwen
This is needed by KVM to make use of VGIC code. Just like regular GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been verified. Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Link: https://lore.kernel.org/r/20240219-cache-v3-2-a33c57534ae9@outlook.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-04-08arm64: dts: hi3798cv200: fix the size of GICRYang Xiwen
During boot, Linux kernel complains: [ 0.000000] GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set This SoC is using a regular GIC-400 and the GICR space size should be 8KB rather than 256B. With this patch: [ 0.000000] GIC: Using split EOI/Deactivate mode So this should be the correct fix. Fixes: 2f20182ed670 ("arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board") Signed-off-by: Yang Xiwen <forbidden405@outlook.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240219-cache-v3-1-a33c57534ae9@outlook.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-08arm64: dts: hisilicon: hikey970-pmic: clean up SPMI nodeJohan Hovold
Clean up the SPMI node by dropping the redundant status property and moving the 'reg' property after 'compatible' for consistency. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-12-08arm64: dts: hisilicon: hikey970-pmic: fix regulator cells propertiesJohan Hovold
The Hi6421 PMIC regulator child nodes do not have unit addresses so drop the incorrect '#address-cells' and '#size-cells' properties. Fixes: 6219b20e1ecd ("arm64: dts: hisilicon: Add support for Hikey 970 PMIC") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-08-03arm64: dts: hi3798cv200: Fix clocks order of sd0David Yang
"ciu" and "biu" were incorrectly swapped. Fix their order. Signed-off-by: David Yang <mmyangfl@gmail.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-07-20arm64: dts: hisilicon: add missing space before {Krzysztof Kozlowski
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-07-20arm64: dts: hisilicon: minor whitespace cleanup around '='Krzysztof Kozlowski
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-06-09Merge tag 'hisi-arm64-dt-for-6.5' of https://github.com/hisilicon/linux-hisi ↵Arnd Bergmann
into soc/dt ARM64: DT: HiSilicon ARM64 DT updates for v6.5 - Clean up the pinctrl-single node names and correct the #size-cells of the pinctrl controller nodes * tag 'hisi-arm64-dt-for-6.5' of https://github.com/hisilicon/linux-hisi: arm64: dts: hisilicon: Unify pinctrl-single pin group nodes Link: https://lore.kernel.org/r/6482C916.1010507@hisilicon.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-07arm64: dts: hisilicon: Unify pinctrl-single pin group nodesTony Lindgren
We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Let's also correct the pinctrl controller #size-cells to 0 while at it. Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-05-16arm64: dts: hisilicon: add missing cache propertiesKrzysztof Kozlowski
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: hi3660-hikey960.dtb: l2-cache0: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223215.115666-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-27arm64: dts: hisilicon: align UART node name with bindingsKrzysztof Kozlowski
Bindings expect UART/serial node names to be "serial". Link: https://lore.kernel.org/r/20230123151516.369130-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-01-13arm64: dts: hisilicon: align LED node names with dtschemaKrzysztof Kozlowski
The node names should be generic and DT schema expects certain pattern: hisilicon/hi3660-hikey960.dtb: leds: wlan_active_led: Unevaluated properties are not allowed ('linux,default-trigger' was unexpected) Link: https://lore.kernel.org/r/20221125144140.477225-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-11-15arm64: dts: Update cache properties for hisiliconPierre Gondois
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2022-06-20arm64: dts: hisilicon: correct gpio-keys propertiesKrzysztof Kozlowski
gpio-keys children do not use unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-10-krzysztof.kozlowski@linaro.org
2022-06-20arm64: dts: hisilicon: align gpio-key node names with dtschemaKrzysztof Kozlowski
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220616005333.18491-9-krzysztof.kozlowski@linaro.org
2022-06-16arm64: dts: hisilicon: adjust whitespace around '='Krzysztof Kozlowski
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204453.832681-1-krzysztof.kozlowski@linaro.org
2022-04-19arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFSKrzysztof Kozlowski
The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220306111125.116455-10-krzysztof.kozlowski@canonical.com
2021-09-22arm64: dts: hisilicon: align operating-points table name with dtschemaKrzysztof Kozlowski
Align the name of operating-points node to dtschema to fix warnings like: cpu_opp_table: $nodename:0: 'cpu_opp_table' does not match '^opp-table(-[a-z0-9]+)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-09-18arm64: dts: hisilicon: fix arm,sp805 compatible stringMichael Walle
According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml the compatible is: compatible = "arm,sp805", "arm,primecell"; The current compatible string doesn't exist at all. Fix it. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-09-18arm64: dts: hisilicon: Add support for Hikey 970 PMICMauro Carvalho Chehab
Add a device tree for the HiSilicon 6421v600 SPMI PMIC, used on HiKey970 board. As we now have support for it, change the fixed regulators used by the SD I/O to use the proper LDO supplies. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-08-13arm64: dts: HiSilicon: hi3660: address a PCI warningMauro Carvalho Chehab
When the driver is registered, it produces a warning when registering the PCI bridge: [ 5.363450] pci_bus 0000:00: root bus resource [bus 00-01] [ 5.396998] pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-01] (conflicts with (null) [bus 00-01]) [ 5.284831] pci 0000:00:00.0: PCI bridge to [bus 01-ff] The reason is that the bus-range is wrong. Address it. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-06-17arm64: dts: hisilicon: use the correct HiSilicon copyrightHao Fang
s/Hisilicon/HiSilicon/. It should use capital S, according to the official website https://www.hisilicon.com/en. Signed-off-by: Hao Fang <fanghao11@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: hi3670.dtsi: add I2C settingsMauro Carvalho Chehab
The I2C buses are not declared at the device tree. As this will be needed by further patches, add them, keeping all in disabled state. Per-board settings can override it. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: hikey970-pinctrl.dtsi: add missing pinctrl settingsMauro Carvalho Chehab
There are several pinctrl settings that are missing at this DT file. Also, the entries are out of order. Add the missing bits, as they'll be required by the DRM driver - and probably by other drivers not upstreamed yet. Reorder the entres, adding the missing bits. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: hi3670.dtsi: add iomcu_rstMauro Carvalho Chehab
This is required in order to support USB. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: delete unused property smmu-cb-memtypeZhen Lei
The "smmu-cb-memtype" is a private property developed by the Hisilicon driver in the early stage and is not used now. So delete it. Otherwise, below YAML check warnings are reported: arch/arm64/boot/dts/hisilicon/hip06-d03.dt.yaml: iommu@a0040000: \ 'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+' arch/arm64/boot/dts/hisilicon/hip07-d05.dt.yaml: iommu@a0040000: \ 'smmu-cb-memtype' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: avoid irrelevant nodes being mistakenly identified as ↵Zhen Lei
PHY nodes Currently, the names of several nodes incorrectly match common PHY provider schema. And the phy-provider.yaml requires them must have property "#phy-cells". As a result, false positives similar to the following are reported: usb2-phy@120: '#phy-cells' is a required property Change their names slightly so that they do not match pattern: "^(|usb-|usb2-|usb3-|pci-|pcie-|sata-)phy(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: normalize the node name of the localbusZhen Lei
Change the node name of the localbus to match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'. This error is detected by simple-bus.yaml. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: normalize the node name of the module thermalZhen Lei
1. Change the node name of the thermal zone to match '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', add suffix "-thermal". 2. Change the node name of the trip point to match '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', delete character "@". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: place clock-names "bus" before "core"Zhen Lei
Look at the clock-names schema defined in arm,mali-utgard.yaml: clock-names: items: - const: bus - const: core The "bus" needs to be placed before the "core". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2021-01-29arm64: dts: hisilicon: separate each group of data in the property "ranges"Zhen Lei
Do not write the "ranges" of multiple groups of data into a uint32 array, use <> to separate them. Otherwise, the errors similar to the following will be reported: soc: pcie@a0090000:ranges: [[33554432, 0, 2986344448, 0, 2986344448, 0, \ 100597760, 16777216, 0, 0, 0, 3086942208, 0, 65536]] is not valid under \ any of the given schemas (Possible causes of the failure): soc: pcie@a0090000:ranges: [[33554432, 0, 2986344448, 0, 2986344448, 0, \ 100597760, 16777216, 0, 0, 0, 3086942208, 0, 65536]] is not of type 'boolean' soc: pcie@a0090000:ranges:0: [33554432, 0, 2986344448, 0, 2986344448, 0, \ 100597760, 16777216, 0, 0, 0, 3086942208, 0, 65536] is too long Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios"Jisheng Zhang
This is to remove similar errors as below: OF: /.../gpio-port@0: could not find phandle Commit 7569486d79ae ("gpio: dwapb: Add ngpios DT-property support") explained the reason of above errors well and added the generic "ngpios" property, let's use it. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hi3660: Harmonize DWC USB3 DT nodes nameSerge Semin
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yamlZhen Lei
The snps,dw-apb-uart binding need to specify two clocks: "baudclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by pl011.yamlZhen Lei
The arm,pl011 binding need to specify two clocks: "uartclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: list all clocks required by spi-pl022.yamlZhen Lei
The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the UART devicesZhen Lei
Change the node name of the UART devices to match "^serial(@[0-9a-f,]+)*$". Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2020-11-24arm64: dts: hisilicon: normalize the node name of the usb devicesZhen Lei
Change the node name of the usb devices to match "^usb(@.*)?". These errors are detected by generic-ehci.yaml and generic-ohci.yaml. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-25 00:07:14 +0000