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A100 perf1 hava MicroSD slot and on-board eMMC module, add support for them.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Link: https://patch.msgid.link/20241031070232.1793078-11-masterr3c0rd@epochal.quest
[wens@csie.org: cherry-picked out of series and GPIO header inclusion added]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The way InvenSense MPU-6050 accelerometer is mounted on the user-facing side
of the Pine64 PinePhone mainboard, which makes it rotated 90 degrees counter-
clockwise, [1] requires the accelerometer's x- and y-axis to be swapped, and
the direction of the accelerometer's y-axis to be inverted.
Rectify this by adding a mount-matrix to the accelerometer definition in the
Pine64 PinePhone dtsi file.
[1] https://files.pine64.org/doc/PinePhone/PinePhone%20mainboard%20bottom%20placement%20v1.1%2020191031.pdf
Fixes: 91f480d40942 ("arm64: dts: allwinner: Add initial support for Pine64 PinePhone")
Cc: stable@vger.kernel.org
Suggested-by: Ondrej Jirman <megi@xff.cz>
Suggested-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Link: https://patch.msgid.link/129f0c754d071cca1db5d207d9d4a7bd9831dff7.1726773282.git.dsimic@manjaro.org
[wens@csie.org: Replaced Helped-by with Suggested-by]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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For lis3mdl, values are based on datasheet and PCB drawing
and tested on a real device.
For af8133j, values are from testing on a real device.
Signed-off-by: Shoji Keita <awaittrot@shjk.jp>
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Link: https://patch.msgid.link/20240908214718.36316-3-andrej.skvortzov@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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New batches of PinePhones switched the magnetometer to AF8133J from
LIS3MDL because lack of ST components.
Both chips use the same PB1 pin, but in different modes.
LIS3MDL uses it as an gpio input to handle interrupt.
AF8133J uses it as an gpio output as a reset signal.
It wasn't possible at runtime to enable both device tree nodes and
detect supported sensor at probe time, because both drivers try to
acquire the same gpio in different modes.
Device tree fixup will be done in firmware without introducing new board
revision and new dts.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Link: https://patchwork.ozlabs.org/project/uboot/patch/20240211092824.395155-1-andrej.skvortzov@gmail.com/
Link: https://patch.msgid.link/20240908214718.36316-2-andrej.skvortzov@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The A100 has 3 MMC controllers, one of them being especially targeted to
eMMC. Let's add nodes on dts.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Link: https://patch.msgid.link/20241031070232.1793078-10-masterr3c0rd@epochal.quest
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The Allwinner A100 has two HCI USB controllers, a OTG controller and a
USB PHY. The PHY is compatible with that used by the D1, while the OTG
controller is compatible with the A33. Add nodes for these to the base
DTSI.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
[masterr3c0rd@epochal.quest: fallback to a33-musb and d1-usb-phy, edited message]
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Parthiban Nallathambi <parthiban@linumiz.com>
Link: https://patch.msgid.link/20241031070232.1793078-7-masterr3c0rd@epochal.quest
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Declare A100's watchdog in the device-tree.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Tested-by: Parthiban Nallathambi <parthiban@linumiz.com>
Link: https://patch.msgid.link/20241031070232.1793078-3-masterr3c0rd@epochal.quest
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add the Performance Monitoring Unit (PMU) device tree node to the A100
.dtsi, which tells DT users which interrupts are triggered by PMU overflow
events on each core.
Signed-off-by: Yangtao Li <frank@allwinnertech.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest>
Link: https://patch.msgid.link/20241031070232.1793078-2-masterr3c0rd@epochal.quest
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Adding disable-wp property for micro SD nodes of Allwinner arm64 devices.
Boards were verified from online pictures/tables
that they have micro SD slots.
Signed-off-by: Kryštof Černý <cleverline1mc@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20240919-b4-nanopineoplus2-fix-mmc0-wp-v2-1-c708a9abc9eb@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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supported boards
Now that the H616 (and variants) audio codec is supported, enable it for
boards with a mainline DTS. The Tanix TX1, Transpeed 8K618-T and X-96
Mate have all been tested with the onboard 3.5mm audio jack and the
Orange Pi Zero 3 with a 3.5mm jack connected to the audio header.
The RG35XX (2024, -H, -Plus and -SP variants) are also tested working
but have a separate mux and GPIO-controlled (PI5) power amplifier to
support both a headphone jack and onboard speakers.
The headphone jack has a GPIO for jack detection, but this is not
currently supported by the driver, so audio is heard both via the
headphone jack and speakers when the speaker amp is powered (by the
CLDO1 regulator, defined as always-on until proper jack detection is
implemented).
Define the audio codec and routing for all supported H616 and variant
boards, and power and speaker amp enablement where present on boards and
known.
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Tested-by: Philippe Simons <simons.philippe@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241023075917.186835-8-ryan@testtoast.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Now that the sun4i codec driver supports the H616, add a node in the
device tree for it (correcting the spdif block location at the same
time).
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20241023075917.186835-7-ryan@testtoast.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Pin controllers pio and r_pio will have proper regulators assigned.
Signed-off-by: Kryštof Černý <cleverline1mc@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240905-nanopi-neo-plus2-regfix-v3-2-1895dff59598@gmail.com
[wens@csie.org: Make "h5" lowercase to match most commits]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Added the main board 5 V supply regulator,
a 2.5 V supply regulator for GMAC PHY IO and correct vin-supply elements.
Signed-off-by: Kryštof Černý <cleverline1mc@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240905-nanopi-neo-plus2-regfix-v3-1-1895dff59598@gmail.com
[wens@csie.org: Make "h5" lowercase to match most commits]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add thermal trips for the two GPU thermal sensors found in the Allwinner A64.
There's only one GPU OPP defined since the commit 1428f0c19f9c ("arm64: dts:
allwinner: a64: Run GPU at 432 MHz"), so defining only the critical thermal
trips makes sense for the A64's two GPU thermal zones.
Having these critical thermal trips defined ensures that no hot spots develop
inside the SoC die that exceed the maximum junction temperature. That might
have been possible before, although quite unlikely, because the CPU and GPU
portions of the SoC are packed closely inside the SoC, so the overheating GPU
would inevitably result in the heat soaking into the CPU portion of the SoC,
causing the CPU thermal sensor to return high readings and trigger the CPU
critical thermal trips. However, it's better not to rely on the heat soak
and have the critical GPU thermal trips properly defined instead.
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Tested-by: Norayr Chilingarian <norayr@arnet.am>
Link: https://lore.kernel.org/r/0a6110a7b27a050bd58ab3663087eecd8e873ac0.1724126053.git.dsimic@manjaro.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add the necessary nodes for the AXP717 to allow for monitoring the USB
and battery charger.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20240821215456.962564-16-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The Anbernic RG35XXSP is almost identical to the RG35XX-Plus, but in a
clamshell form-factor. The key differences between the SP and the Plus
is a lid switch and an RTC on the same i2c bus as the PMIC.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240710231718.106894-5-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Change the Anbernic RG35XX series to use the r_i2c bus for the PMIC
instead of the r_rsb bus. This is to keep the device tree consistent
as there are at least 3 devices (the RG35XX-SP, RG28XX, and RG40XX-H)
that have an external RTC on the r_i2c bus.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Ryan Walklin <ryan@testtoast.com>
Link: https://lore.kernel.org/r/20240710231718.106894-4-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add pinctrl nodes for the r_i2c node. Without the pinmux defined the
r_i2c bus may fail to work, possibly if the bootloader uses rsb mode
for the PMIC.
Fixes: 0d17c8651188 ("arm64: dts: allwinner: Add Allwinner H616 .dtsi file")
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Fixes: 0d17c8651188 ("arm64: dts: allwinner: Add Allwinner H616 .dtsi file")
Link: https://lore.kernel.org/r/20240710231718.106894-3-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Pull SoC dt updates from Arnd Bergmann:
"The devicetree updates are fairly well spread out across platforms,
with Qualcomm making up about a third of the total.
There are three new SoCs in existing product families this:
- NXP i.MX95 is a variant of i.MX93, now with six Cortex-A55 cores
instead of just two as well as a GPU and more high-speed I/O
devices.
- Qualcomm QCS8550 is a variant of SM8550 for IOT devices
- Airoha EN7581 is a 10G-PON network chip and related to the MT7981
Wireless router chip from its parent Mediatek.
In total there are 58 new machines, including four riscv boards and
eight for 32-bit arm.
The most exciting new addition is probably a pair of laptops based on
the Qualcomm x1e80100 (Snapdragon X1 Elite) chip, the Asus Vivobook
S15 and the Lenovo Yoga Slim7x.
Other noteworthy new additions are:
- A total of 20 Qualcomm based machines, mostly Android devices from
Samsung, Motorola and LG, as well as a wireless router and some
reference designs
- Six NXP i.MX based machines, mostly industrial boards along with
some reference designs
- Mediatek sees some interesting Filogic based routers including the
"OpenWRT One", a few new Chromebooks as well as single-board
computers.
- Four machines from Solidrun based on Marvell cn913x, replacing the
older Armada 8000 based counterparts
- The four Amlogic machines are all set top boxes or reference
designs for them
- The nine new Rockchips machines are mostly single-board computers
including some interesting ones based on the rk3588 chip like the
ROCK 5 ITX board and the CM3588 with its four NVMe slots
- The RISC-V boards are all single-board computers based on Starfive
JH7110, Microchip MPFS and Allwinner D1, which all had similar
boards already
There are also a lot of updates to already supported machines, notably
for the TI K3, Rockchips, Freescale and of course Qualcomm platforms"
* tag 'soc-dt-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (846 commits)
arm64: dts: allwinner: h616: add crypto engine node
riscv: dts: add clock generator for Sophgo SG2042 SoC
arm64: dts: rockchip: Add Xunlong Orange Pi 3B
dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B
arm64: dts: rockchip: Add Radxa ROCK 3B
dt-bindings: arm: rockchip: Add Radxa ROCK 3B
mailmap: Update Luca Weiss's email address
ARM: dts: ixp4xx: nslu2: beeper uses PWM
arm64: dts: rockchip: add ROCK 5 ITX board
dt-bindings: arm: rockchip: Add ROCK 5 ITX board
arm64: dts: rockchip: Add dma-names to uart1 on Pine64 rk3566 devices
arm64: dts: rockchip: Add avdd supplies to hdmi on rock64
arm64: dts: qcom: msm8916-lg-c50: add initial dts for LG Leon LTE
arm64: dts: qcom: msm8916-lg-m216: Add initial device tree
dt-bindings: arm: qcom: Add msm8916 based LG devices
ARM: dts: qcom: msm8960: correct memory base
arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
dt-bindings: interconnect: Add Qualcomm IPQ9574 support
arm64: dts: qcom: sm8150: Add video clock controller node
arm64: dts: qcom: pm6150: Add vibrator
...
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The Allwinner H616 SoC contains a crypto engine very similar to the H6
version, but with all base addresses in the DMA descriptors shifted by
two bits. This requires a new compatible string.
Also the H616 CE relies on the internal osciallator for the TRNG
operation, so we need to reference this clock.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240624232110.9817-5-andre.przywara@arm.com
[wens@csie.org: fix up register range size]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The Allwinner H616 contains a scatter-gather IOMMU connected to some
video related devices. It's almost compatible to the one used in the H6,
though with minor incompatibilities.
Add the DT node describing its resources, so that devices like the video
or display engine can connect to it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Ryan Walklin <ryan@testtoast.com>
Link: https://lore.kernel.org/r/20240616224056.29159-6-andre.przywara@arm.com
[wens@csie.org: Move IOMMU node after GIC node for address order]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The Anbernic RG35XX device variants (-2024, -H, -Plus and -SP) are the
only currently known devices to have an Allwinner H700 SoC. The closely
related RG28XX also has the H700 but a mainline DT for this device has
not yet been submitted.
Include the H616 CPU OPP table in the base device DTS, and increase the
DCDC1 regulator (vdd-cpu) upper voltage range to 1.16V, allowing the
CPU to reach 1.5GHz.
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Tested-by: Philippe Simons <simons.philippe@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240607092140.33112-4-ryan@testtoast.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The H700 now shows stable operation with the 1.008, 1.032 and 1.512 GHz
DVFS operating points. The 1.5GHz OPP requires a VDD-CPU of 1.16V,
obtained from the vendor BSP. This voltage is slightly above the
recommended operating voltage for the H616 (H700 datasheet not publicly
available) but well within the absolute maximum of 1.3V.
Add the additional 1.032 GHz operating point to the H616 CPU-OPP table,
and enable the 1.008 and 1.512 points for the H700.
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Tested-by: Philippe Simons <simons.philippe@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240607092140.33112-3-ryan@testtoast.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add support for the ADC joysticks found on the Anbernic RG35XX-H. The
joysticks use one channel of the GPADC which is muxed 4 ways by an ADC
mux.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20240605172049.231108-5-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The H616 has a GPADC controller which is identical to the one found on
the D1/T113s/R329/T507 SoCs.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Link: https://lore.kernel.org/r/20240605172049.231108-4-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add missing cache information to the Allwinner H616 SoC dtsi, to allow
the userspace, which includes lscpu(1) that uses the virtual files provided
by the kernel under the /sys/devices/system/cpu directory, to display the
proper H616 cache information.
Adding the cache information to the H616 SoC dtsi also makes the following
warning message in the kernel log go away:
cacheinfo: Unable to detect cache hierarchy for CPU 0
Rather conspicuously, almost no cache-related information is available in
the publicly available Allwinner H616 datasheet (version 1.0) and H616 user
manual (version 1.0). Thus, the cache parameters for the H616 SoC dtsi were
obtained and derived by hand from the cache size and layout specifications
found in the following technical reference manual, and from the cache size
and die revision hints available from the following community-provided data
and memory subsystem benchmarks:
- ARM Cortex-A53 revision r0p4 TRM, version J
- Summary of the two available H616 die revisions and their differences
in cache sizes observed from the CSSIDR_EL1 register readouts, provided
by Andre Przywara [1][2]
- Tinymembench benchmark results of the H616-based OrangePi Zero 2 SBC,
provided by Thomas Kaiser [3]
For future reference, here's a brief summary of the available documentation
and the community-provided data and memory subsystem benchmarks:
- All caches employ the 64-byte cache line length
- Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
cache and 32 KB of L1 4-way, set-associative data cache
- The size of the L2 cache depends on the actual H616 die revision (there
are two die revisions), so the entire SoC can have either 256 KB or 1 MB
of unified L2 16-way, set-associative cache [1]
Also for future reference, here's the relevant excerpt from the community-
provided H616 memory subsystem benchmark, [3] which confirms that 32 KB and
256 KB are the L1 data and L2 cache sizes, respectively:
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.3 ns / 7.3 ns
131072 : 6.6 ns / 10.5 ns
262144 : 9.8 ns / 15.2 ns
524288 : 91.8 ns / 142.9 ns
1048576 : 138.6 ns / 188.3 ns
2097152 : 163.0 ns / 204.8 ns
4194304 : 178.8 ns / 213.5 ns
8388608 : 187.1 ns / 217.9 ns
16777216 : 192.2 ns / 220.9 ns
33554432 : 196.5 ns / 224.0 ns
67108864 : 215.7 ns / 259.5 ns
The changes introduced to the H616 SoC dtsi by this patch specify 256 KB as
the L2 cache size. As outlined by Andre Przywara, [2] a follow-up TF-A patch
will perform runtime adjustment of the device tree data, making the correct
L2 cache size of 1 MB present in the device tree for the boards based on the
revision of H616 that actually provides 1 MB of L2 cache.
[1] https://lore.kernel.org/linux-sunxi/20240430114627.0cfcd14a@donnerap.manchester.arm.com/
[2] https://lore.kernel.org/linux-sunxi/20240501103059.10a8f7de@donnerap.manchester.arm.com/
[3] https://raw.githubusercontent.com/ThomasKaiser/sbc-bench/master/results/4knM.txt
Suggested-by: Andre Przywara <andre.przywara@arm.com>
Helped-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/e4b9cc3e3d366a571e552c31dafa5de847bc1c12.1716914537.git.dsimic@manjaro.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add missing cache information to the Allwinner A64 SoC dtsi, to allow
the userspace, which includes lscpu(1) that uses the virtual files provided
by the kernel under the /sys/devices/system/cpu directory, to display the
proper A64 cache information.
While there, use a more self-descriptive label for the L2 cache node, which
also makes it more consistent with other SoC dtsi files.
The cache parameters for the A64 dtsi were obtained and partially derived
by hand from the cache size and layout specifications found in the following
datasheets and technical reference manuals:
- Allwinner A64 datasheet, version 1.1
- ARM Cortex-A53 revision r0p3 TRM, version E
For future reference, here's a brief summary of the documentation:
- All caches employ the 64-byte cache line length
- Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
cache and 32 KB of L1 4-way, set-associative data cache
- The entire SoC has 512 KB of unified L2 16-way, set-associative cache
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/6a772756c2c677dbdaaab4a2c71a358d8e4b27e9.1714304058.git.dsimic@manjaro.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Correct the model names of a few Pine64 boards and devices, according
to their official names used in the Pine64 wiki and on the official Pine64
website. [1][2][3] This ensures consistency between the officially used
names and the names in the source code.
[1] https://wiki.pine64.org/wiki/PINE_A64
[2] https://wiki.pine64.org/wiki/PINE_H64
[3] https://pine64.org/devices/
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Marek Kraus <gamiee@pine64.org>
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Link: https://lore.kernel.org/r/4a988518e0dba5de3ecfc172a0fa2b0653c00d8b.1716768092.git.dsimic@manjaro.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add missing cache information to the Allwinner H6 SoC dtsi, to allow
the userspace, which includes lscpu(1) that uses the virtual files provided
by the kernel under the /sys/devices/system/cpu directory, to display the
proper H6 cache information.
Adding the cache information to the H6 SoC dtsi also makes the following
warning message in the kernel log go away:
cacheinfo: Unable to detect cache hierarchy for CPU 0
The cache parameters for the H6 dtsi were obtained and partially derived
by hand from the cache size and layout specifications found in the following
datasheets and technical reference manuals:
- Allwinner H6 V200 datasheet, version 1.1
- ARM Cortex-A53 revision r0p3 TRM, version E
For future reference, here's a brief summary of the documentation:
- All caches employ the 64-byte cache line length
- Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
cache and 32 KB of L1 4-way, set-associative data cache
- The entire SoC has 512 KB of unified L2 16-way, set-associative cache
Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add a DT node for the Allwinner H616 LRADC describing the base address,
interrupt, reset and clock gates.
Signed-off-by: James McGregor <jamcgregor@protonmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Škrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240426092924.15489-3-jamcgregor@protonmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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The "r_intc" interrupt controller on the A64 uses a mapping scheme, so
the first (and only) NMI interrupt #0 appears as interrupt number 32
(cf. the top comment in drivers/irqchip/irq-sun6i-r.c).
Fix that number in the interrupts property to properly forward PMIC
interrupts to the CPU.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fixes: 4d39a8eb07eb ("arm64: dts: allwinner: Add Jide Remix Mini PC support")
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20240515234852.26929-1-andre.przywara@arm.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull power management updates from Rafael Wysocki:
"These are mostly cpufreq updates, including a significant intel-pstate
driver update and several amd-pstate improvements plus some updates of
ARM cpufreq drivers, general fixes and cleanups.
Also included are changes related to system sleep, power capping
updates adding support for a new platform and a new hardware feature
(among other things), a Samsung exynos-asv driver update allowing it
to change its Energy Model after adjusting voltage, minor cpuidle and
devfreq updates and a small documentation cleanup.
Specifics:
- Rework the handling of disabled turbo in the intel_pstate driver
and make it update the maximum CPU frequency consistently
regardless of the reason on top of a number of cleanups (Rafael
Wysocki)
- Add missing checks for NULL .exit() cpufreq driver callback to the
cpufreq core (Viresh Kumar)
- Prevent pulicy->max from going above the frequency QoS maximum
value when cpufreq_frequency_table_verify() is used (Xuewen Yan)
- Prevent a negative CPU number or frequency value from being printed
if they are really large (Joshua Yeong)
- Update MAINTAINERS entry for amd-pstate to add two new
submaintainers and a designated reviewer (Huang Rui)
- Clean up the amd-pstate driver and update its documentation
(Gautham Shenoy)
- Fix the highest frequency issue in the amd-pstate driver which
limits performance (Perry Yuan)
- Enable CPPC v2 for certain processors in the family 17H, as
requested by TR40 processor users who expect improved performance
and lower system temperature (Perry Yuan)
- Change latency and delay values to be read from platform firmware
firstly for more accurate timing (Perry Yuan)
- A new quirk is introduced for supporting amd-pstate on legacy
processors which either lack CPPC capability, or only only have
CPPC v2 capability (Perry Yuan)
- Sun50i cpufreq: Add support for opp_supported_hw, H616 platform and
general cleanups (Andre Przywara, Martin Botka, Brandon Cheo Fusi,
Dan Carpenter, Viresh Kumar)
- CPPC cpufreq: Fix possible null pointer dereference (Aleksandr
Mishin)
- Eliminate uses of of_node_put() from cpufreq (Javier Carrasco,
Shivani Gupta)
- brcmstb-avs: ISO C90 forbids mixed declarations (Portia Stephens)
- mediatek cpufreq: Add support for MT7988A (Sam Shih)
- cpufreq-qcom-hw: Add SM4450 compatibles in DT bindings (Tengfei
Fan)
- Fix struct cpudata::epp_cached kernel-doc in the intel_pstate
cpufreq driver (Jeff Johnson)
- Fix kerneldoc description of ladder_do_selection() (Jeff Johnson)
- Convert the cpuidle kirkwood driver to platform remove callback
returning void (Yangtao Li)
- Replace deprecated strncpy() with strscpy() in the hibernation core
code (Justin Stitt)
- Use %ps to simplify debug output in the core system-wide suspend
and resume code (Len Brown)
- Remove unnecessary else from device_init_wakeup() and make
device_wakeup_disable() return void (Dhruva Gole)
- Enable PMU support in the Intel TPMI RAPL driver (Zhang Rui)
- Add support for ArrowLake-H platform to the Intel RAPL driver
(Zhang Rui)
- Avoid explicit cpumask allocation on stack in DTPM (Dawei Li)
- Make the Samsung exynos-asv driver update the Energy Model after
adjusting voltage on top of some preliminary changes of the OPP and
Enery Model generic code (Lukasz Luba)
- Remove a reference to a function that has been dropped from the
power management documentation (Bjorn Helgaas)
- Convert the platfrom remove callback to .remove_new for the
exyno-nocp, exynos-ppmu, mtk-cci-devfreq, sun8i-a33-mbus, and
rk3399_dmc devfreq drivers (Uwe Kleine-König)
- Use DEFINE_SIMPLE_PM_OPS for exyno-bus.c driver (Anand Moon)"
* tag 'pm-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (68 commits)
PM / devfreq: exynos: Use DEFINE_SIMPLE_DEV_PM_OPS for PM functions
PM / devfreq: rk3399_dmc: Convert to platform remove callback returning void
PM / devfreq: sun8i-a33-mbus: Convert to platform remove callback returning void
PM / devfreq: mtk-cci: Convert to platform remove callback returning void
PM / devfreq: exynos-ppmu: Convert to platform remove callback returning void
PM / devfreq: exynos-nocp: Convert to platform remove callback returning void
cpufreq: amd-pstate: fix the highest frequency issue which limits performance
cpufreq: intel_pstate: fix struct cpudata::epp_cached kernel-doc
cpuidle: ladder: fix ladder_do_selection() kernel-doc
powercap: intel_rapl_tpmi: Enable PMU support
powercap: intel_rapl: Introduce APIs for PMU support
PM: hibernate: replace deprecated strncpy() with strscpy()
cpufreq: Fix up printing large CPU numbers and frequency values
MAINTAINERS: cpufreq: amd-pstate: Add co-maintainers and reviewer
cpufreq: amd-pstate: remove unused variable lowest_nonlinear_freq
cpufreq: amd-pstate: fix code format problems
cpufreq: amd-pstate: Add quirk for the pstate CPPC capabilities missing
cppc_acpi: print error message if CPPC is unsupported
cpufreq: amd-pstate: get transition delay and latency value from ACPI tables
cpufreq: amd-pstate: Bail out if min/max/nominal_freq is 0
...
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The RG35XX-H adds thumbsticks, a stereo speaker, and a second USB port to
the RG35XX-Plus, and has a horizontal form factor.
Enabled in this DTS:
- Thumbsticks
- Second USB port
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240427110225.727472-8-ryan@testtoast.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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The RG35XX-Plus adds a RTL8221CS SDIO Wifi/BT chip to the RG35XX (2024).
Enabled in this DTS:
- WiFi
- Bluetooth
- Supporting power sequence and GPIOs
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240427110225.727472-7-ryan@testtoast.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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The base model RG35XX (2024) is a handheld gaming device based on an
Allwinner H700 chip.
The H700 is a H616 variant (4x ARM Cortex-A53 cores @ 1.5Ghz with Mali G31
GPU) which exposes RGB LCD and NMI pins.
Device features:
- Allwinner H700 @ 1.5GHz
- 1GB LPDDR4 DRAM
- X-Powers AXP717 PMIC
- 3.5" 640x480 RGB LCD
- Two microSD slots
- Mini-HDMI out
- GPIO keypad
- 3.5mm headphone jack
- USB-C charging port
Enabled in this DTS:
- AXP717 PMIC with RSB serial interface, regulators and NMI interrupt
controller
- Power LED (charge LED on device controlled directly by PMIC)
- Serial UART (accessible from headers on the board)
- First SD slot (SD2 appears to have a GPIO-switched regulator for 1.8v
low-voltage signalling, this is not yet modeled. Enablement with a
switched regulator will be confirmed and posted in a follow-up patch).
Signed-off-by: Ryan Walklin <ryan@testtoast.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240427110225.727472-6-ryan@testtoast.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Add device node for the H616 Non Maskable Interrupt (NMI) controller.
This controller is present on all H616 boards and derivatives such as
the T507 and H700. Note that on the H616 no NMI pad is exposed.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240418181615.1370179-3-macroalpha82@gmail.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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The Tanix TX1 is a tiny TV box with the Allwinner H313 SoC. The box
features no Ethernet or an SD card slot, which makes booting from it
somewhat interesting: Pressing the hidden FEL button and using a USB-A
to USB-A cable to upload code from a host PC is one way to run mainline.
The box features:
- Allwinner H313 SoC (4 * Arm Cortex-A53 cores)
- 1 or 2 GB DRAM
- 8 or 16 GB eMMC flash
- SCI S9082H WiFi chip
- HDMI port
- one USB 2.0 port
- 3.5mm AV port
- barrel plug 5V DC input via barrel plug
The devicetree covers most peripherals.
The eMMC did not work properly in HS200 speed mode, so this mode property
is omitted. HS-DDR seems to work fine.
The blue LED is connected to the same GPIO pin as the red LED, just
using the opposite polarity. Apparently there is no way of describing
this in DT, so the red LED is omitted.
Next to the FEL button is a hidden button, that can be pushed by using
something like a paperclip, through the ventilation vents of the case.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240418104942.1556914-3-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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With the DT bindings now describing the format of the CPU OPP tables, we
can include the OPP table in each board's .dts file, and specify the CPU
power supply.
This allows to enable DVFS, and get up to 50% of performance benefit in
the highest OPP, or up to 60% power savings in the lowest OPP, compared
to the fixed 1GHz @ 1.0V OPP we are running in by default at the moment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Add an Operating Performance Points table for the CPU cores to enable
Dynamic Voltage & Frequency Scaling (DVFS) on the H616.
The values were taken from the BSP sources. There is a separate OPP set
seen on some H700 devices, but they didn't really work out in testing, so
they are not included for now.
Also add the needed cpu_speed_grade nvmem cell and the cooling cells
properties, to enable passive cooling.
Signed-off-by: Martin Botka <martin.botka@somainline.org>
[Andre: rework to minimise opp-microvolt properties]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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Currently we specify the pins for the I2C0 function as PI6 and PI7, even
though they are actually PI5 and PI6. Linux' pinctrl driver and the H616
user manual confirm this.
Fix the pin names in the pins property. None of the existing DTs in the
tree seems to use I2C0, which explains why this went unnoticed.
Fixes: 0d17c8651188 ("arm64: dts: allwinner: Add Allwinner H616 .dtsi file")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240329103825.25463-1-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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The Allwinner A64's GPU has currently three operating points. However,
the BSP runs the GPU fixed at 432 MHz. In addition, at least one of the
devices using that SoC - the pinephone - shows unstabilities (see link)
that can be circumvented by running the GPU at a fixed rate.
Therefore, remove the other two operating points from the GPU OPP table,
so that the GPU runs at a fixed rate of 432 MHz.
Link: https://gitlab.com/postmarketOS/pmaports/-/issues/805
Acked-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-5-46fc80c83637@oltmanns.dev
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Underscores should not be used in node names (dtc with W=2 warns about
them), so replace them with hyphens. Use also generic name for pwrseq
node, because generic naming is favored by Devicetree spec. All the
clocks affected by this change use clock-output-names, so resulting
clock name should not change. Functional impact checked with comparing
before/after DTBs with dtx_diff and fdtdump.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240317184130.157695-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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There is no "reg_gmac_3v3" device node in sun50i-h6-pine-h64.dts,
although there is "gmac-3v3" with "reg_gmac_3v3" label, so let's assume
author wanted to remove that node. Delete node via phandle, not via
full node path, to fix this.
Fixes: f33a91175029 ("arm64: dts: allwinner: add pineh64 model B")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240317184130.157695-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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The red, green, and blue LEDs currently in the device tree represent a
single RGB LED on the front of the PinePhone.
Signed-off-by: Aren Moynihan <aren@peacevolution.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240317004116.1473967-2-aren@peacevolution.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Allows user to set a LED before entering suspend to know that
the phone is still on (or could be used for notifications etc).
Signed-off-by: Miles Alan <m@milesalan.com>
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Signed-off-by: Aren Moynihan <aren@peacevolution.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240317004116.1473967-1-aren@peacevolution.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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There are four thermal sensors:
- CPU
- GPU
- VE
- DRAM
Add the thermal sensor configuration and the thermal zones.
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240219153639.179814-8-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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The Sipeed Longan SoM 3H is a system on module based on the Allwinner
H618 SoC. The SoM features:
- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
- 2/4 GiB LPDDR4 DRAM SoMs
- AXP313a PMIC
- eMMC
The Sipeed Longan PI 3H is a development board based on the above SoM.
The board features:
- Longan SoM 3H
- Raspberry-Pi-1 compatible GPIO header
- 2 USB 2.0 host port
- 1 USB 2.0 type C port (power supply + OTG)
- MicroSD slot
- 1Gbps Ethernet port (via RTL8211 PHY)
- HDMI port
- WiFi/BT chip
Add the devicetree file describing the currently supported features,
namely PMIC, LEDs, UART, SD card, eMMC, USB and Ethernet.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240211081739.395-3-jszhang@kernel.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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The DTS code coding style expects exactly one space before '{'
character.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240208105301.129005-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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Documentation/process/license-rules.rst and checkpatch expect the SPDX
identifier syntax for multiple licenses to use capital "OR". Correct it
to keep consistent format and avoid copy-paste issues.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240208105301.129005-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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In contrast to other devices using Allwinner SoCs, the Transpeed 8K618-T
TV box uses a mainline supported WiFi chip: it's Broadcom 4335 compatible,
packaged by Murata.
Add the required DT nodes to let DT users know about the SDIO device.
There is an otherwise empty MMC device node, to receive the MAC address,
that firmware might want to write in there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20240209115759.3582869-3-andre.przywara@arm.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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