diff options
Diffstat (limited to 'drivers/gpu/drm/radeon')
25 files changed, 172 insertions, 260 deletions
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c index c1bbfbe28bda..ceb6d772ef94 100644 --- a/drivers/gpu/drm/radeon/atom.c +++ b/drivers/gpu/drm/radeon/atom.c @@ -68,8 +68,8 @@ typedef struct { } atom_exec_context; int atom_debug = 0; -static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); -int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); +static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params); +int atom_execute_table(struct atom_context *ctx, int index, uint32_t *params); static uint32_t atom_arg_mask[8] = { 0xFFFFFFFF, 0x0000FFFF, 0x00FFFF00, 0xFFFF0000, @@ -163,13 +163,9 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base, ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 3)); temp |= - ((ctx-> - io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - - CU8 - (base - + - 1)))) - << CU8(base + 3); + ((ctx->io_attr >> CU8(base + 2)) & + (0xFFFFFFFF >> (32 - CU8(base + 1)))) << + CU8(base + 3); base += 4; break; case ATOM_IIO_END: @@ -1156,7 +1152,7 @@ static struct { atom_op_shr, ATOM_ARG_MC}, { atom_op_debug, 0},}; -static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) +static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params) { int base = CU16(ctx->cmd_table + 4 + 2 * index); int len, ws, ps, ptr; @@ -1216,7 +1212,7 @@ free: return ret; } -int atom_execute_table_scratch_unlocked(struct atom_context *ctx, int index, uint32_t * params) +int atom_execute_table_scratch_unlocked(struct atom_context *ctx, int index, uint32_t *params) { int r; @@ -1237,7 +1233,7 @@ int atom_execute_table_scratch_unlocked(struct atom_context *ctx, int index, uin return r; } -int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) +int atom_execute_table(struct atom_context *ctx, int index, uint32_t *params) { int r; mutex_lock(&ctx->scratch_mutex); @@ -1359,8 +1355,8 @@ void atom_destroy(struct atom_context *ctx) } bool atom_parse_data_header(struct atom_context *ctx, int index, - uint16_t * size, uint8_t * frev, uint8_t * crev, - uint16_t * data_start) + uint16_t *size, uint8_t *frev, uint8_t *crev, + uint16_t *data_start) { int offset = index * 2 + 4; int idx = CU16(ctx->data_table + offset); @@ -1379,8 +1375,8 @@ bool atom_parse_data_header(struct atom_context *ctx, int index, return true; } -bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, - uint8_t * crev) +bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev, + uint8_t *crev) { int offset = index * 2 + 4; int idx = CU16(ctx->cmd_table + offset); diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 5d6b81a6578e..10be30366c2b 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9534,17 +9534,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &bridge_cfg); - pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, - &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, - tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -9591,21 +9582,14 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) msleep(100); /* linkctl */ - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(root, PCI_EXP_LNKCTL, - tmp16); - - pcie_capability_read_word(rdev->pdev, - PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(rdev->pdev, - PCI_EXP_LNKCTL, - tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); /* linkctl2 */ pcie_capability_read_word(root, PCI_EXP_LNKCTL2, diff --git a/drivers/gpu/drm/radeon/clearstate_si.h b/drivers/gpu/drm/radeon/clearstate_si.h index 356219c6c7f2..7da8418704fe 100644 --- a/drivers/gpu/drm/radeon/clearstate_si.h +++ b/drivers/gpu/drm/radeon/clearstate_si.h @@ -23,8 +23,7 @@ #include "clearstate_defs.h" -static const u32 si_SECT_CONTEXT_def_1[] = -{ +static const u32 si_SECT_CONTEXT_def_1[] = { 0x00000000, // DB_RENDER_CONTROL 0x00000000, // DB_COUNT_CONTROL 0x00000000, // DB_DEPTH_VIEW diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 9c1a92fa2af6..25201b9a5aae 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c @@ -249,7 +249,7 @@ void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) /* Sub pixel 1/12 so we can have 4K rendering according to doc */ gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); - switch(rdev->num_gb_pipes) { + switch (rdev->num_gb_pipes) { case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; @@ -638,7 +638,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, track = (struct r100_cs_track *)p->track; idx_value = radeon_get_ib_value(p, idx); - switch(reg) { + switch (reg) { case AVIVO_D1MODE_VLINE_START_END: case RADEON_CRTC_GUI_TRIG_VLINE: r = r100_cs_packet_parse_vline(p); @@ -1180,7 +1180,7 @@ static int r300_packet3_check(struct radeon_cs_parser *p, ib = p->ib.ptr; idx = pkt->idx + 1; track = (struct r100_cs_track *)p->track; - switch(pkt->opcode) { + switch (pkt->opcode) { case PACKET3_3D_LOAD_VBPNTR: r = r100_packet3_load_vbpntr(p, pkt, idx); if (r) diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c b/drivers/gpu/drm/radeon/radeon_acpi.c index 5771d1fcb073..603a78e41ba5 100644 --- a/drivers/gpu/drm/radeon/radeon_acpi.c +++ b/drivers/gpu/drm/radeon/radeon_acpi.c @@ -618,7 +618,7 @@ int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, atcs_input.size = sizeof(struct atcs_pref_req_input); /* client id (bit 2-0: func num, 7-3: dev num, 15-8: bus num) */ - atcs_input.client_id = rdev->pdev->devfn | (rdev->pdev->bus->number << 8); + atcs_input.client_id = pci_dev_id(rdev->pdev); atcs_input.valid_flags_mask = ATCS_VALID_FLAGS_MASK; atcs_input.flags = ATCS_WAIT_FOR_COMPLETION; if (advertise) diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c index d124600b5f58..a3d749e350f9 100644 --- a/drivers/gpu/drm/radeon/radeon_agp.c +++ b/drivers/gpu/drm/radeon/radeon_agp.c @@ -130,7 +130,7 @@ static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev) { struct pci_dev *pdev = to_pci_dev(dev->dev); - struct radeon_agp_head *head = NULL; + struct radeon_agp_head *head; head = kzalloc(sizeof(*head), GFP_KERNEL); if (!head) diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index bf3c411a55c5..85c4bb186203 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -1389,7 +1389,7 @@ bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); - ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) + ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) ((u8 *)&ss_info->asSS_Info[0]); for (i = 0; i < num_indices; i++) { if (ss_assign->ucSS_Id == id) { @@ -1402,7 +1402,7 @@ bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, ss->refdiv = ss_assign->ucRecommendedRef_Div; return true; } - ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*) + ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *) ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT)); } } @@ -3406,7 +3406,7 @@ static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT { u32 size = le16_to_cpu(v2->sHeader.usStructureSize); u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]); - u8 *start = (u8*)v2; + u8 *start = (u8 *)v2; while (offset < size) { ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset); @@ -3423,7 +3423,7 @@ static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT { u32 size = le16_to_cpu(v3->sHeader.usStructureSize); u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); - u8 *start = (u8*)v3; + u8 *start = (u8 *)v3; while (offset < size) { ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c index d0b450a06506..595354e3ce0b 100644 --- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c +++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c @@ -115,7 +115,7 @@ static union acpi_object *radeon_atpx_call(acpi_handle handle, int function, /* Fail only if calling the method fails and ATPX is supported */ if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) { - printk("failed to evaluate ATPX got %s\n", + pr_err("failed to evaluate ATPX got %s\n", acpi_format_exception(status)); kfree(buffer.pointer); return NULL; @@ -171,7 +171,7 @@ static int radeon_atpx_validate(struct radeon_atpx *atpx) size = *(u16 *) info->buffer.pointer; if (size < 10) { - printk("ATPX buffer is too small: %zu\n", size); + pr_err("ATPX buffer is too small: %zu\n", size); kfree(info); return -EINVAL; } @@ -202,7 +202,7 @@ static int radeon_atpx_validate(struct radeon_atpx *atpx) atpx->is_hybrid = false; if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) { - printk("ATPX Hybrid Graphics\n"); + pr_info("ATPX Hybrid Graphics\n"); /* * Disable legacy PM methods only when pcie port PM is usable, * otherwise the device might fail to power off or power on. @@ -239,7 +239,7 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx) size = *(u16 *) info->buffer.pointer; if (size < 8) { - printk("ATPX buffer is too small: %zu\n", size); + pr_err("ATPX buffer is too small: %zu\n", size); err = -EINVAL; goto out; } @@ -248,8 +248,8 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx) memcpy(&output, info->buffer.pointer, size); /* TODO: check version? */ - printk("ATPX version %u, functions 0x%08x\n", - output.version, output.function_bits); + pr_info("ATPX version %u, functions 0x%08x\n", + output.version, output.function_bits); radeon_atpx_parse_functions(&atpx->functions, output.function_bits); diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c index 795c3667f6d6..2620efc7c675 100644 --- a/drivers/gpu/drm/radeon/radeon_combios.c +++ b/drivers/gpu/drm/radeon/radeon_combios.c @@ -863,7 +863,7 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct struct radeon_device *rdev = dev->dev_private; uint16_t dac_info; uint8_t rev, bg, dac; - struct radeon_encoder_primary_dac *p_dac = NULL; + struct radeon_encoder_primary_dac *p_dac; int found = 0; p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), @@ -1014,7 +1014,7 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct struct radeon_device *rdev = dev->dev_private; uint16_t dac_info; uint8_t rev, bg, dac; - struct radeon_encoder_tv_dac *tv_dac = NULL; + struct radeon_encoder_tv_dac *tv_dac; int found = 0; tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); @@ -1100,7 +1100,7 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct radeon_device *rdev) { - struct radeon_encoder_lvds *lvds = NULL; + struct radeon_encoder_lvds *lvds; uint32_t fp_vert_stretch, fp_horz_stretch; uint32_t ppll_div_sel, ppll_val; uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 07193cd0c417..d2f02c3dfce2 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -198,8 +198,7 @@ int radeon_get_monitor_bpc(struct drm_connector *connector) DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", connector->name, bpc); } - } - else if (bpc > 8) { + } else if (bpc > 8) { /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", connector->name); @@ -334,10 +333,8 @@ static void radeon_connector_free_edid(struct drm_connector *connector) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); - if (radeon_connector->edid) { - kfree(radeon_connector->edid); - radeon_connector->edid = NULL; - } + kfree(radeon_connector->edid); + radeon_connector->edid = NULL; } static int radeon_ddc_get_modes(struct drm_connector *connector) @@ -1372,7 +1369,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) /* assume digital unless load detected otherwise */ radeon_connector->use_digital = true; lret = encoder_funcs->detect(encoder, connector); - DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); + DRM_DEBUG_KMS("load_detect %x returned: %x\n", encoder->encoder_type, lret); if (lret == connector_status_connected) radeon_connector->use_digital = false; } diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 39cdede460b5..fa531493b111 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -113,59 +113,32 @@ #define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MINOR 50 #define KMS_DRIVER_PATCHLEVEL 0 -int radeon_suspend_kms(struct drm_device *dev, bool suspend, - bool fbcon, bool freeze); -int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); -extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, - unsigned int flags, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode); -extern bool radeon_is_px(struct drm_device *dev); -int radeon_mode_dumb_mmap(struct drm_file *filp, - struct drm_device *dev, - uint32_t handle, uint64_t *offset_p); -int radeon_mode_dumb_create(struct drm_file *file_priv, - struct drm_device *dev, - struct drm_mode_create_dumb *args); - -/* atpx handler */ -#if defined(CONFIG_VGA_SWITCHEROO) -void radeon_register_atpx_handler(void); -void radeon_unregister_atpx_handler(void); -bool radeon_has_atpx_dgpu_power_cntl(void); -bool radeon_is_atpx_hybrid(void); -#else -static inline void radeon_register_atpx_handler(void) {} -static inline void radeon_unregister_atpx_handler(void) {} -static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } -static inline bool radeon_is_atpx_hybrid(void) { return false; } -#endif int radeon_no_wb; int radeon_modeset = -1; int radeon_dynclks = -1; -int radeon_r4xx_atom = 0; +int radeon_r4xx_atom; int radeon_agpmode = -1; -int radeon_vram_limit = 0; +int radeon_vram_limit; int radeon_gart_size = -1; /* auto */ -int radeon_benchmarking = 0; -int radeon_testing = 0; -int radeon_connector_table = 0; +int radeon_benchmarking; +int radeon_testing; +int radeon_connector_table; int radeon_tv = 1; int radeon_audio = -1; -int radeon_disp_priority = 0; -int radeon_hw_i2c = 0; +int radeon_disp_priority; +int radeon_hw_i2c; int radeon_pcie_gen2 = -1; int radeon_msi = -1; int radeon_lockup_timeout = 10000; -int radeon_fastfb = 0; +int radeon_fastfb; int radeon_dpm = -1; int radeon_aspm = -1; int radeon_runtime_pm = -1; -int radeon_hard_reset = 0; +int radeon_hard_reset; int radeon_vm_size = 8; int radeon_vm_block_size = -1; -int radeon_deep_color = 0; +int radeon_deep_color; int radeon_use_pflipirq = 2; int radeon_bapm = -1; int radeon_backlight = -1; @@ -384,6 +357,7 @@ radeon_pci_shutdown(struct pci_dev *pdev) static int radeon_pmops_suspend(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); + return radeon_suspend_kms(drm_dev, true, true, false); } @@ -404,12 +378,14 @@ static int radeon_pmops_resume(struct device *dev) static int radeon_pmops_freeze(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); + return radeon_suspend_kms(drm_dev, false, true, true); } static int radeon_pmops_thaw(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); + return radeon_resume_kms(drm_dev, false, true); } @@ -494,6 +470,7 @@ long radeon_drm_ioctl(struct file *filp, struct drm_file *file_priv = filp->private_data; struct drm_device *dev; long ret; + dev = file_priv->minor->dev; ret = pm_runtime_get_sync(dev->dev); if (ret < 0) { diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 2ffe0975ee54..34a1c73d3938 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -124,4 +124,17 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); void radeon_driver_postclose_kms(struct drm_device *dev, struct drm_file *file_priv); +/* atpx handler */ +#if defined(CONFIG_VGA_SWITCHEROO) +void radeon_register_atpx_handler(void); +void radeon_unregister_atpx_handler(void); +bool radeon_has_atpx_dgpu_power_cntl(void); +bool radeon_is_atpx_hybrid(void); +#else +static inline void radeon_register_atpx_handler(void) {} +static inline void radeon_unregister_atpx_handler(void) {} +static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } +static inline bool radeon_is_atpx_hybrid(void) { return false; } +#endif + #endif /* __RADEON_DRV_H__ */ diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c index b3518a8f95a0..9cb6401fe97e 100644 --- a/drivers/gpu/drm/radeon/radeon_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_encoders.c @@ -58,6 +58,7 @@ static uint32_t radeon_encoder_clones(struct drm_encoder *encoder) count = -1; list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) { struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder); + count++; if (clone_encoder == encoder) @@ -108,9 +109,10 @@ radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8 if (ASIC_IS_AVIVO(rdev)) ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1; else { - /*if (rdev->family == CHIP_R200) - ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; - else*/ + /* if (rdev->family == CHIP_R200) + * ret = ENCODER_INTERNAL_DVO1_ENUM_ID1; + * else + */ ret = ENCODER_INTERNAL_DAC2_ENUM_ID1; } break; @@ -234,6 +236,7 @@ void radeon_encoder_set_active_device(struct drm_encoder *encoder) list_for_each_entry(connector, &dev->mode_config.connector_list, head) { if (connector->encoder == encoder) { struct radeon_connector *radeon_connector = to_radeon_connector(connector); + radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices; DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n", radeon_encoder->active_device, radeon_encoder->devices, @@ -320,12 +323,12 @@ void radeon_panel_mode_fixup(struct drm_encoder *encoder, struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; struct drm_display_mode *native_mode = &radeon_encoder->native_mode; - unsigned hblank = native_mode->htotal - native_mode->hdisplay; - unsigned vblank = native_mode->vtotal - native_mode->vdisplay; - unsigned hover = native_mode->hsync_start - native_mode->hdisplay; - unsigned vover = native_mode->vsync_start - native_mode->vdisplay; - unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start; - unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start; + unsigned int hblank = native_mode->htotal - native_mode->hdisplay; + unsigned int vblank = native_mode->vtotal - native_mode->vdisplay; + unsigned int hover = native_mode->hsync_start - native_mode->hdisplay; + unsigned int vover = native_mode->vsync_start - native_mode->vdisplay; + unsigned int hsync_width = native_mode->hsync_end - native_mode->hsync_start; + unsigned int vsync_width = native_mode->vsync_end - native_mode->vsync_start; adjusted_mode->clock = native_mode->clock; adjusted_mode->flags = native_mode->flags; @@ -424,6 +427,7 @@ bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, bool radeon_encoder_is_digital(struct drm_encoder *encoder) { struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); + switch (radeon_encoder->encoder_id) { case ENCODER_OBJECT_ID_INTERNAL_LVDS: case ENCODER_OBJECT_ID_INTERNAL_TMDS1: diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c index 04109a2a6fd7..4bb242437ff6 100644 --- a/drivers/gpu/drm/radeon/radeon_gart.c +++ b/drivers/gpu/drm/radeon/radeon_gart.c @@ -74,9 +74,9 @@ int radeon_gart_table_ram_alloc(struct radeon_device *rdev) ptr = dma_alloc_coherent(&rdev->pdev->dev, rdev->gart.table_size, &rdev->gart.table_addr, GFP_KERNEL); - if (ptr == NULL) { + if (!ptr) return -ENOMEM; - } + #ifdef CONFIG_X86 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { @@ -99,9 +99,9 @@ int radeon_gart_table_ram_alloc(struct radeon_device *rdev) */ void radeon_gart_table_ram_free(struct radeon_device *rdev) { - if (rdev->gart.ptr == NULL) { + if (!rdev->gart.ptr) return; - } + #ifdef CONFIG_X86 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { @@ -133,9 +133,8 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev) r = radeon_bo_create(rdev, rdev->gart.table_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 0, NULL, NULL, &rdev->gart.robj); - if (r) { + if (r) return r; - } } return 0; } @@ -197,9 +196,9 @@ void radeon_gart_table_vram_unpin(struct radeon_device *rdev) { int r; - if (rdev->gart.robj == NULL) { + if (!rdev->gart.robj) return; - } + r = radeon_bo_reserve(rdev->gart.robj, false); if (likely(r == 0)) { radeon_bo_kunmap(rdev->gart.robj); @@ -220,9 +219,9 @@ void radeon_gart_table_vram_unpin(struct radeon_device *rdev) */ void radeon_gart_table_vram_free(struct radeon_device *rdev) { - if (rdev->gart.robj == NULL) { + if (!rdev->gart.robj) return; - } + radeon_bo_unref(&rdev->gart.robj); } @@ -239,11 +238,10 @@ void radeon_gart_table_vram_free(struct radeon_device *rdev) * Unbinds the requested pages from the gart page table and * replaces them with the dummy page (all asics). */ -void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, +void radeon_gart_unbind(struct radeon_device *rdev, unsigned int offset, int pages) { - unsigned t; - unsigned p; + unsigned int t, p; int i, j; if (!rdev->gart.ready) { @@ -284,12 +282,11 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, * (all asics). * Returns 0 for success, -EINVAL for failure. */ -int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, +int radeon_gart_bind(struct radeon_device *rdev, unsigned int offset, int pages, struct page **pagelist, dma_addr_t *dma_addr, uint32_t flags) { - unsigned t; - unsigned p; + unsigned int t, p; uint64_t page_base, page_entry; int i, j; @@ -307,9 +304,9 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) { page_entry = radeon_gart_get_page_entry(page_base, flags); rdev->gart.pages_entry[t] = page_entry; - if (rdev->gart.ptr) { + if (rdev->gart.ptr) radeon_gart_set_page(rdev, t, page_entry); - } + page_base += RADEON_GPU_PAGE_SIZE; } } @@ -332,9 +329,9 @@ int radeon_gart_init(struct radeon_device *rdev) { int r, i; - if (rdev->gart.pages) { + if (rdev->gart.pages) return 0; - } + /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */ if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) { DRM_ERROR("Page size is smaller than GPU page size!\n"); diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index d0119c5f7eb3..358d19242f4b 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -316,7 +316,7 @@ int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, { /* TODO: implement */ DRM_ERROR("unimplemented %s\n", __func__); - return -ENOSYS; + return -EOPNOTSUPP; } int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, @@ -324,7 +324,7 @@ int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, { /* TODO: implement */ DRM_ERROR("unimplemented %s\n", __func__); - return -ENOSYS; + return -EOPNOTSUPP; } int radeon_gem_create_ioctl(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index e0214cf1b43b..a16590c6247f 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -444,7 +444,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); return -EINVAL; } - value = (uint32_t*)&value64; + value = (uint32_t *)&value64; value_size = sizeof(uint64_t); value64 = radeon_get_gpu_clock_counter(rdev); break; @@ -543,18 +543,18 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) *value = rdev->vce.fb_version; break; case RADEON_INFO_NUM_BYTES_MOVED: - value = (uint32_t*)&value64; + value = (uint32_t *)&value64; value_size = sizeof(uint64_t); value64 = atomic64_read(&rdev->num_bytes_moved); break; case RADEON_INFO_VRAM_USAGE: - value = (uint32_t*)&value64; + value = (uint32_t *)&value64; value_size = sizeof(uint64_t); man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); value64 = ttm_resource_manager_usage(man); break; case RADEON_INFO_GTT_USAGE: - value = (uint32_t*)&value64; + value = (uint32_t *)&value64; value_size = sizeof(uint64_t); man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_TT); value64 = ttm_resource_manager_usage(man); @@ -614,7 +614,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) DRM_DEBUG_KMS("Invalid request %d\n", info->request); return -EINVAL; } - if (copy_to_user(value_ptr, (char*)value, value_size)) { + if (copy_to_user(value_ptr, (char *)value, value_size)) { DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); return -EFAULT; } diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c index 601d35d34eab..c4350ac2b3d2 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c @@ -1692,7 +1692,7 @@ static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon { struct drm_device *dev = encoder->base.dev; struct radeon_device *rdev = dev->dev_private; - struct radeon_encoder_int_tmds *tmds = NULL; + struct radeon_encoder_int_tmds *tmds; bool ret; tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); @@ -1715,7 +1715,7 @@ static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct ra { struct drm_device *dev = encoder->base.dev; struct radeon_device *rdev = dev->dev_private; - struct radeon_encoder_ext_tmds *tmds = NULL; + struct radeon_encoder_ext_tmds *tmds; bool ret; if (rdev->is_atom_bios) diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c index 12e180b119ac..7883e9ec0bae 100644 --- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c +++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c @@ -724,12 +724,14 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, } for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { - if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) + tv_dac->tv.h_code_timing[i] = hor_timing[i]; + if (tv_dac->tv.h_code_timing[i] == 0) break; } for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { - if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) + tv_dac->tv.v_code_timing[i] = vert_timing[i]; + if (tv_dac->tv.v_code_timing[i] == 0) break; } diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c index c87a57c9c592..22dd8b445685 100644 --- a/drivers/gpu/drm/radeon/radeon_sa.c +++ b/drivers/gpu/drm/radeon/radeon_sa.c @@ -123,7 +123,7 @@ int radeon_sa_bo_new(struct radeon_sa_manager *sa_manager, unsigned int size, unsigned int align) { struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size, - GFP_KERNEL, true, align); + GFP_KERNEL, false, align); if (IS_ERR(sa)) { *sa_bo = NULL; diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c index a5e1d2139e80..c9fef9b61ced 100644 --- a/drivers/gpu/drm/radeon/radeon_test.c +++ b/drivers/gpu/drm/radeon/radeon_test.c @@ -156,10 +156,10 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag) i, *vram_start, gtt_start, (unsigned long long) (gtt_addr - rdev->mc.gtt_start + - (void*)gtt_start - gtt_map), + (void *)gtt_start - gtt_map), (unsigned long long) (vram_addr - rdev->mc.vram_start + - (void*)gtt_start - gtt_map)); + (void *)gtt_start - gtt_map)); radeon_bo_kunmap(vram_obj); goto out_lclean_unpin; } @@ -207,10 +207,10 @@ static void radeon_do_test_moves(struct radeon_device *rdev, int flag) i, *gtt_start, vram_start, (unsigned long long) (vram_addr - rdev->mc.vram_start + - (void*)vram_start - vram_map), + (void *)vram_start - vram_map), (unsigned long long) (gtt_addr - rdev->mc.gtt_start + - (void*)vram_start - vram_map)); + (void *)vram_start - vram_map)); radeon_bo_kunmap(gtt_obj[i]); goto out_lclean_unpin; } diff --git a/drivers/gpu/drm/radeon/radeon_vce.c b/drivers/gpu/drm/radeon/radeon_vce.c index ca4a36464340..d1871af967d4 100644 --- a/drivers/gpu/drm/radeon/radeon_vce.c +++ b/drivers/gpu/drm/radeon/radeon_vce.c @@ -95,7 +95,7 @@ int radeon_vce_init(struct radeon_device *rdev) size = rdev->vce_fw->size - strlen(fw_version) - 9; c = rdev->vce_fw->data; - for (;size > 0; --size, ++c) + for (; size > 0; --size, ++c) if (strncmp(c, fw_version, strlen(fw_version)) == 0) break; @@ -110,7 +110,7 @@ int radeon_vce_init(struct radeon_device *rdev) size = rdev->vce_fw->size - strlen(fb_version) - 3; c = rdev->vce_fw->data; - for (;size > 0; --size, ++c) + for (; size > 0; --size, ++c) if (strncmp(c, fb_version, strlen(fb_version)) == 0) break; diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 26fa9b095514..9ce12fa3c356 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -136,8 +136,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) return 0; } -static const u32 r7xx_golden_registers[] = -{ +static const u32 r7xx_golden_registers[] = { 0x8d00, 0xffffffff, 0x0e0e0074, 0x8d04, 0xffffffff, 0x013a2b34, 0x9508, 0xffffffff, 0x00000002, @@ -152,8 +151,7 @@ static const u32 r7xx_golden_registers[] = 0x7300, 0xffffffff, 0x001000f0 }; -static const u32 r7xx_golden_dyn_gpr_registers[] = -{ +static const u32 r7xx_golden_dyn_gpr_registers[] = { 0x8db0, 0xffffffff, 0x98989898, 0x8db4, 0xffffffff, 0x98989898, 0x8db8, 0xffffffff, 0x98989898, @@ -165,8 +163,7 @@ static const u32 r7xx_golden_dyn_gpr_registers[] = 0x88c4, 0xffffffff, 0x00000082 }; -static const u32 rv770_golden_registers[] = -{ +static const u32 rv770_golden_registers[] = { 0x562c, 0xffffffff, 0, 0x3f90, 0xffffffff, 0, 0x9148, 0xffffffff, 0, @@ -175,8 +172,7 @@ static const u32 rv770_golden_registers[] = 0x9698, 0x18000000, 0x18000000 }; -static const u32 rv770ce_golden_registers[] = -{ +static const u32 rv770ce_golden_registers[] = { 0x562c, 0xffffffff, 0, 0x3f90, 0xffffffff, 0x00cc0000, 0x9148, 0xffffffff, 0x00cc0000, @@ -187,8 +183,7 @@ static const u32 rv770ce_golden_registers[] = 0x9698, 0x18000000, 0x18000000 }; -static const u32 rv770_mgcg_init[] = -{ +static const u32 rv770_mgcg_init[] = { 0x8bcc, 0xffffffff, 0x130300f9, 0x5448, 0xffffffff, 0x100, 0x55e4, 0xffffffff, 0x100, @@ -345,8 +340,7 @@ static const u32 rv770_mgcg_init[] = 0x92a4, 0xffffffff, 0x00080007 }; -static const u32 rv710_golden_registers[] = -{ +static const u32 rv710_golden_registers[] = { 0x3f90, 0x00ff0000, 0x00fc0000, 0x9148, 0x00ff0000, 0x00fc0000, 0x3f94, 0x00ff0000, 0x00fc0000, @@ -355,8 +349,7 @@ static const u32 rv710_golden_registers[] = 0xa180, 0xffffffff, 0x00003f3f }; -static const u32 rv710_mgcg_init[] = -{ +static const u32 rv710_mgcg_init[] = { 0x8bcc, 0xffffffff, 0x13030040, 0x5448, 0xffffffff, 0x100, 0x55e4, 0xffffffff, 0x100, @@ -414,8 +407,7 @@ static const u32 rv710_mgcg_init[] = 0x9150, 0xffffffff, 0x4d940000 }; -static const u32 rv730_golden_registers[] = -{ +static const u32 rv730_golden_registers[] = { 0x3f90, 0x00ff0000, 0x00f00000, 0x9148, 0x00ff0000, 0x00f00000, 0x3f94, 0x00ff0000, 0x00f00000, @@ -425,8 +417,7 @@ static const u32 rv730_golden_registers[] = 0xa180, 0xffffffff, 0x00003f3f }; -static const u32 rv730_mgcg_init[] = -{ +static const u32 rv730_mgcg_init[] = { 0x8bcc, 0xffffffff, 0x130300f9, 0x5448, 0xffffffff, 0x100, 0x55e4, 0xffffffff, 0x100, @@ -547,8 +538,7 @@ static const u32 rv730_mgcg_init[] = 0x92a4, 0xffffffff, 0x00000005 }; -static const u32 rv740_golden_registers[] = -{ +static const u32 rv740_golden_registers[] = { 0x88c4, 0xffffffff, 0x00000082, 0x28a50, 0xfffffffc, 0x00000004, 0x2650, 0x00040000, 0, @@ -584,8 +574,7 @@ static const u32 rv740_golden_registers[] = 0x9698, 0x18000000, 0x18000000 }; -static const u32 rv740_mgcg_init[] = -{ +static const u32 rv740_mgcg_init[] = { 0x8bcc, 0xffffffff, 0x13030100, 0x5448, 0xffffffff, 0x100, 0x55e4, 0xffffffff, 0x100, diff --git a/drivers/gpu/drm/radeon/rv770_smc.c b/drivers/gpu/drm/radeon/rv770_smc.c index 45575c0d0a1d..09fa7f5e7c41 100644 --- a/drivers/gpu/drm/radeon/rv770_smc.c +++ b/drivers/gpu/drm/radeon/rv770_smc.c @@ -34,8 +34,7 @@ #define FIRST_SMC_INT_VECT_REG 0xFFD8 #define FIRST_INT_VECT_S19 0xFFC0 -static const u8 rv770_smc_int_vectors[] = -{ +static const u8 rv770_smc_int_vectors[] = { 0x08, 0x10, 0x08, 0x10, 0x08, 0x10, 0x08, 0x10, 0x08, 0x10, 0x08, 0x10, @@ -54,8 +53,7 @@ static const u8 rv770_smc_int_vectors[] = 0x03, 0x51, 0x03, 0x51 }; -static const u8 rv730_smc_int_vectors[] = -{ +static const u8 rv730_smc_int_vectors[] = { 0x08, 0x15, 0x08, 0x15, 0x08, 0x15, 0x08, 0x15, 0x08, 0x15, 0x08, 0x15, @@ -74,8 +72,7 @@ static const u8 rv730_smc_int_vectors[] = 0x03, 0x56, 0x03, 0x56 }; -static const u8 rv710_smc_int_vectors[] = -{ +static const u8 rv710_smc_int_vectors[] = { 0x08, 0x04, 0x08, 0x04, 0x08, 0x04, 0x08, 0x04, 0x08, 0x04, 0x08, 0x04, @@ -94,8 +91,7 @@ static const u8 rv710_smc_int_vectors[] = 0x03, 0x51, 0x03, 0x51 }; -static const u8 rv740_smc_int_vectors[] = -{ +static const u8 rv740_smc_int_vectors[] = { 0x08, 0x10, 0x08, 0x10, 0x08, 0x10, 0x08, 0x10, 0x08, 0x10, 0x08, 0x10, @@ -114,8 +110,7 @@ static const u8 rv740_smc_int_vectors[] = 0x03, 0x51, 0x03, 0x51 }; -static const u8 cedar_smc_int_vectors[] = -{ +static const u8 cedar_smc_int_vectors[] = { 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, @@ -134,8 +129,7 @@ static const u8 cedar_smc_int_vectors[] = 0x04, 0xF6, 0x04, 0xF6 }; -static const u8 redwood_smc_int_vectors[] = -{ +static const u8 redwood_smc_int_vectors[] = { 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, @@ -154,8 +148,7 @@ static const u8 redwood_smc_int_vectors[] = 0x04, 0xF6, 0x04, 0xF6 }; -static const u8 juniper_smc_int_vectors[] = -{ +static const u8 juniper_smc_int_vectors[] = { 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, @@ -174,8 +167,7 @@ static const u8 juniper_smc_int_vectors[] = 0x04, 0xF6, 0x04, 0xF6 }; -static const u8 cypress_smc_int_vectors[] = -{ +static const u8 cypress_smc_int_vectors[] = { 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, 0x0B, 0x05, @@ -194,8 +186,7 @@ static const u8 cypress_smc_int_vectors[] = 0x04, 0xF6, 0x04, 0xF6 }; -static const u8 barts_smc_int_vectors[] = -{ +static const u8 barts_smc_int_vectors[] = { 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, @@ -214,8 +205,7 @@ static const u8 barts_smc_int_vectors[] = 0x05, 0x0A, 0x05, 0x0A }; -static const u8 turks_smc_int_vectors[] = -{ +static const u8 turks_smc_int_vectors[] = { 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, @@ -234,8 +224,7 @@ static const u8 turks_smc_int_vectors[] = 0x05, 0x0A, 0x05, 0x0A }; -static const u8 caicos_smc_int_vectors[] = -{ +static const u8 caicos_smc_int_vectors[] = { 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, 0x0C, 0x14, @@ -254,8 +243,7 @@ static const u8 caicos_smc_int_vectors[] = 0x05, 0x0A, 0x05, 0x0A }; -static const u8 cayman_smc_int_vectors[] = -{ +static const u8 cayman_smc_int_vectors[] = { 0x12, 0x05, 0x12, 0x05, 0x12, 0x05, 0x12, 0x05, 0x12, 0x05, 0x12, 0x05, diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 8d5e4b25609d..a91012447b56 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -7131,17 +7131,8 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &bridge_cfg); - pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, - &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, - tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -7188,22 +7179,14 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) msleep(100); /* linkctl */ - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(root, - PCI_EXP_LNKCTL, - tmp16); - - pcie_capability_read_word(rdev->pdev, - PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(rdev->pdev, - PCI_EXP_LNKCTL, - tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); /* linkctl2 */ pcie_capability_read_word(root, PCI_EXP_LNKCTL2, diff --git a/drivers/gpu/drm/radeon/sislands_smc.h b/drivers/gpu/drm/radeon/sislands_smc.h index 4ea1cb2e45a3..4b7dee3cf58b 100644 --- a/drivers/gpu/drm/radeon/sislands_smc.h +++ b/drivers/gpu/drm/radeon/sislands_smc.h @@ -89,8 +89,7 @@ struct PP_SIslands_PAPMStatus }; typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus; -struct PP_SIslands_PAPMParameters -{ +struct PP_SIslands_PAPMParameters { uint32_t NearTDPLimitTherm; uint32_t NearTDPLimitPAPM; uint32_t PlatformPowerLimit; @@ -100,8 +99,7 @@ struct PP_SIslands_PAPMParameters }; typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters; -struct SISLANDS_SMC_SCLK_VALUE -{ +struct SISLANDS_SMC_SCLK_VALUE { uint32_t vCG_SPLL_FUNC_CNTL; uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t vCG_SPLL_FUNC_CNTL_3; @@ -113,8 +111,7 @@ struct SISLANDS_SMC_SCLK_VALUE typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE; -struct SISLANDS_SMC_MCLK_VALUE -{ +struct SISLANDS_SMC_MCLK_VALUE { uint32_t vMPLL_FUNC_CNTL; uint32_t vMPLL_FUNC_CNTL_1; uint32_t vMPLL_FUNC_CNTL_2; @@ -129,8 +126,7 @@ struct SISLANDS_SMC_MCLK_VALUE typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE; -struct SISLANDS_SMC_VOLTAGE_VALUE -{ +struct SISLANDS_SMC_VOLTAGE_VALUE { uint16_t value; uint8_t index; uint8_t phase_settings; @@ -138,8 +134,7 @@ struct SISLANDS_SMC_VOLTAGE_VALUE typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE; -struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL -{ +struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL { uint8_t ACIndex; uint8_t displayWatermark; uint8_t gen2PCIE; @@ -180,8 +175,7 @@ struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL; -struct SISLANDS_SMC_SWSTATE -{ +struct SISLANDS_SMC_SWSTATE { uint8_t flags; uint8_t levelCount; uint8_t padding2; @@ -205,8 +199,7 @@ struct SISLANDS_SMC_SWSTATE_SINGLE { #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3 #define SISLANDS_SMC_VOLTAGEMASK_MAX 4 -struct SISLANDS_SMC_VOLTAGEMASKTABLE -{ +struct SISLANDS_SMC_VOLTAGEMASKTABLE { uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; }; @@ -214,8 +207,7 @@ typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; #define SISLANDS_MAX_NO_VREG_STEPS 32 -struct SISLANDS_SMC_STATETABLE -{ +struct SISLANDS_SMC_STATETABLE { uint8_t thermalProtectType; uint8_t systemFlags; uint8_t maxVDDCIndexInPPTable; @@ -254,8 +246,7 @@ typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE; #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120 -struct PP_SIslands_FanTable -{ +struct PP_SIslands_FanTable { uint8_t fdo_mode; uint8_t padding; int16_t temp_min; @@ -285,8 +276,7 @@ typedef struct PP_SIslands_FanTable PP_SIslands_FanTable; #define SMC_SISLANDS_SCALE_I 7 #define SMC_SISLANDS_SCALE_R 12 -struct PP_SIslands_CacConfig -{ +struct PP_SIslands_CacConfig { uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; uint32_t lkge_lut_V0; uint32_t lkge_lut_Vstep; @@ -308,23 +298,20 @@ typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig; #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 -struct SMC_SIslands_MCRegisterAddress -{ +struct SMC_SIslands_MCRegisterAddress { uint16_t s0; uint16_t s1; }; typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress; -struct SMC_SIslands_MCRegisterSet -{ +struct SMC_SIslands_MCRegisterSet { uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; }; typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet; -struct SMC_SIslands_MCRegisters -{ +struct SMC_SIslands_MCRegisters { uint8_t last; uint8_t reserved[3]; SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; @@ -333,8 +320,7 @@ struct SMC_SIslands_MCRegisters typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters; -struct SMC_SIslands_MCArbDramTimingRegisterSet -{ +struct SMC_SIslands_MCArbDramTimingRegisterSet { uint32_t mc_arb_dram_timing; uint32_t mc_arb_dram_timing2; uint8_t mc_arb_rfsh_rate; @@ -344,8 +330,7 @@ struct SMC_SIslands_MCArbDramTimingRegisterSet typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet; -struct SMC_SIslands_MCArbDramTimingRegisters -{ +struct SMC_SIslands_MCArbDramTimingRegisters { uint8_t arb_current; uint8_t reserved[3]; SMC_SIslands_MCArbDramTimingRegisterSet data[16]; @@ -353,8 +338,7 @@ struct SMC_SIslands_MCArbDramTimingRegisters typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters; -struct SMC_SISLANDS_SPLL_DIV_TABLE -{ +struct SMC_SISLANDS_SPLL_DIV_TABLE { uint32_t freq[256]; uint32_t ss[256]; }; @@ -374,8 +358,7 @@ typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE; #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16 -struct Smc_SIslands_DTE_Configuration -{ +struct Smc_SIslands_DTE_Configuration { uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; uint32_t K; |