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path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.h
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Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_cx0_phy.h')
-rw-r--r--drivers/gpu/drm/i915/display/intel_cx0_phy.h17
1 files changed, 8 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index f99809af257d..912e0eeb0be3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -10,14 +10,15 @@
#include <linux/bitfield.h>
#include <linux/bits.h>
-#include "i915_drv.h"
-#include "intel_display_types.h"
-
-struct drm_i915_private;
-struct intel_encoder;
-struct intel_crtc_state;
enum icl_port_dpll_id;
enum phy;
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_c10pll_state;
+struct intel_c20pll_state;
+struct intel_crtc_state;
+struct intel_encoder;
+struct intel_hdmi;
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
@@ -43,8 +44,6 @@ int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
-void intel_cx0_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- u32 level);
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
+
#endif /* __INTEL_CX0_PHY_H__ */