6 files changed, 27 insertions, 75 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
index 785236a44aee..1ecb54603e17 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h
@@ -20,7 +20,7 @@ struct core_dc {
 	struct dc_context *ctx;
 
 	uint8_t link_count;
-	struct core_link *links[MAX_PIPES * 2];
+	struct dc_link *links[MAX_PIPES * 2];
 
 	struct validate_context *current_context;
 	struct resource_pool *res_pool;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 07a1aec5a28b..6cdfeeba0faf 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -92,13 +92,11 @@ struct core_sink {
 
 	/** The 'protected' area - read/write access, for use only inside DC **/
 	/* not used for now */
-	struct core_link *link;
+	struct dc_link *link;
 	struct dc_context *ctx;
 };
 
 /************ link *****************/
-#define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public)
-
 struct link_init_data {
 	const struct core_dc *dc;
 	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
@@ -107,61 +105,15 @@ struct link_init_data {
 				TODO: remove it when DC is complete. */
 };
 
-/* DP MST stream allocation (payload bandwidth number) */
-struct link_mst_stream_allocation {
-	/* DIG front */
-	const struct stream_encoder *stream_enc;
-	/* associate DRM payload table with DC stream encoder */
-	uint8_t vcp_id;
-	/* number of slots required for the DP stream in transport packet */
-	uint8_t slot_count;
-};
-
-/* DP MST stream allocation table */
-struct link_mst_stream_allocation_table {
-	/* number of DP video streams */
-	int stream_count;
-	/* array of stream allocations */
-	struct link_mst_stream_allocation
-	stream_allocations[MAX_CONTROLLER_NUM];
-};
-
-struct core_link {
-	struct dc_link public;
-	const struct core_dc *dc;
-
-	struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/
-
-	struct link_encoder *link_enc;
-	struct graphics_object_id link_id;
-	union ddi_channel_mapping ddi_channel_mapping;
-	struct connector_device_tag_info device_tag;
-	struct dpcd_caps dpcd_caps;
-	unsigned int dpcd_sink_count;
-
-	enum edp_revision edp_revision;
-	bool psr_enabled;
-
-	/* MST record stream using this link */
-	struct link_flags {
-		bool dp_keep_receiver_powered;
-	} wa_flags;
-	struct link_mst_stream_allocation_table mst_stream_alloc_table;
-
-	struct dc_link_status link_status;
-};
-
-#define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public)
-
-struct core_link *link_create(const struct link_init_data *init_params);
-void link_destroy(struct core_link **link);
+struct dc_link *link_create(const struct link_init_data *init_params);
+void link_destroy(struct dc_link **link);
 
 enum dc_status dc_link_validate_mode_timing(
 		const struct core_stream *stream,
-		struct core_link *link,
+		struct dc_link *link,
 		const struct dc_crtc_timing *timing);
 
-void core_link_resume(struct core_link *link);
+void core_link_resume(struct dc_link *link);
 
 void core_link_enable_stream(struct pipe_ctx *pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 9c2f670c3dc3..af7ea5eaf185 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -84,7 +84,7 @@ void dal_ddc_aux_payloads_add(
 struct ddc_service_init_data {
 	struct graphics_object_id id;
 	struct dc_context *ctx;
-	struct core_link *link;
+	struct dc_link *link;
 };
 
 struct ddc_service *dal_ddc_service_create(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index b6ef1bfd267c..d9af028a39df 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -29,12 +29,12 @@
 #define LINK_TRAINING_ATTEMPTS 4
 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
 
-struct core_link;
+struct dc_link;
 struct core_stream;
 struct dc_link_settings;
 
 bool dp_hbr_verify_link_cap(
-	struct core_link *link,
+	struct dc_link *link,
 	struct dc_link_settings *known_limit_link_setting);
 
 bool decide_fallback_link_setting(struct dc_link_settings link_setting_init,
@@ -46,7 +46,7 @@ struct dc_link_settings get_common_supported_link_settings (
 		struct dc_link_settings link_setting_b);
 
 bool dp_validate_mode_timing(
-	struct core_link *link,
+	struct dc_link *link,
 	const struct dc_crtc_timing *timing);
 
 void decide_link_settings(
@@ -54,17 +54,17 @@ void decide_link_settings(
 	struct dc_link_settings *link_setting);
 
 bool perform_link_training_with_retries(
-	struct core_link *link,
+	struct dc_link *link,
 	const struct dc_link_settings *link_setting,
 	bool skip_video_pattern,
 	int attempts);
 
-bool is_mst_supported(struct core_link *link);
+bool is_mst_supported(struct dc_link *link);
 
-void detect_dp_sink_caps(struct core_link *link);
+void detect_dp_sink_caps(struct dc_link *link);
 
-bool is_dp_active_dongle(const struct core_link *link);
+bool is_dp_active_dongle(const struct dc_link *link);
 
-void dp_enable_mst_on_sink(struct core_link *link, bool enable);
+void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
 
 #endif /* __DC_LINK_DP_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
index 6067f464d805..e34b25939a98 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h
@@ -39,7 +39,7 @@ struct dmcu_funcs {
 			unsigned int bytes);
 	void (*set_psr_enable)(struct dmcu *dmcu, bool enable);
 	void (*setup_psr)(struct dmcu *dmcu,
-			struct core_link *link,
+			struct dc_link *link,
 			struct psr_context *psr_context);
 	void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state);
 	void (*set_psr_wait_loop)(struct dmcu *dmcu,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 75d10e93b002..f7994cfc850d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -29,46 +29,46 @@
 #include "inc/core_status.h"
 
 enum dc_status core_link_read_dpcd(
-	struct core_link* link,
+	struct dc_link *link,
 	uint32_t address,
 	uint8_t *data,
 	uint32_t size);
 
 enum dc_status core_link_write_dpcd(
-	struct core_link* link,
+	struct dc_link *link,
 	uint32_t address,
 	const uint8_t *data,
 	uint32_t size);
 
 void dp_enable_link_phy(
-	struct core_link *link,
+	struct dc_link *link,
 	enum signal_type signal,
 	enum clock_source_id clock_source,
 	const struct dc_link_settings *link_settings);
 
-void dp_receiver_power_ctrl(struct core_link *link, bool on);
+void dp_receiver_power_ctrl(struct dc_link *link, bool on);
 
-void dp_disable_link_phy(struct core_link *link, enum signal_type signal);
+void dp_disable_link_phy(struct dc_link *link, enum signal_type signal);
 
-void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal);
+void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal);
 
 bool dp_set_hw_training_pattern(
-	struct core_link *link,
+	struct dc_link *link,
 	enum hw_dp_training_pattern pattern);
 
 void dp_set_hw_lane_settings(
-	struct core_link *link,
+	struct dc_link *link,
 	const struct link_training_settings *link_settings);
 
 void dp_set_hw_test_pattern(
-	struct core_link *link,
+	struct dc_link *link,
 	enum dp_test_pattern test_pattern,
 	uint8_t *custom_pattern,
 	uint32_t custom_pattern_size);
 
-enum dp_panel_mode dp_get_panel_mode(struct core_link *link);
+enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
 
-void dp_retrain_link_dp_test(struct core_link *link,
+void dp_retrain_link_dp_test(struct dc_link *link,
 		struct dc_link_settings *link_setting,
 		bool skip_video_pattern);