diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
25 files changed, 3694 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h new file mode 100644 index 000000000000..f9b871b6199b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h @@ -0,0 +1,503 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +/** + * Bandwidth and Watermark calculations interface. + * (Refer to "DCEx_mode_support.xlsm" from Perforce.) + */ +#ifndef __BANDWIDTH_CALCS_H__ +#define __BANDWIDTH_CALCS_H__ + +#include "bw_fixed.h" + +struct pipe_ctx; + +enum bw_calcs_version { + BW_CALCS_VERSION_INVALID, + BW_CALCS_VERSION_CARRIZO, + BW_CALCS_VERSION_POLARIS10, + BW_CALCS_VERSION_POLARIS11, + BW_CALCS_VERSION_STONEY, +}; + +/******************************************************************************* + * There are three types of input into Calculations: + * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP + * 2. board-level values - these are generally coming from VBIOS parser + * 3. mode/configuration values - depending Mode, Scaling number of Displays etc. + ******************************************************************************/ + +enum bw_defines { + //Common + bw_def_no = 0, + bw_def_none = 0, + bw_def_yes = 1, + bw_def_ok = 1, + bw_def_high = 2, + bw_def_mid = 1, + bw_def_low = 0, + + //Internal + bw_defs_start = 255, + bw_def_underlay422, + bw_def_underlay420_luma, + bw_def_underlay420_chroma, + bw_def_underlay444, + bw_def_graphics, + bw_def_display_write_back420_luma, + bw_def_display_write_back420_chroma, + bw_def_portrait, + bw_def_hsr_mtn_4, + bw_def_hsr_mtn_h_taps, + bw_def_ceiling__h_taps_div_4___meq_hsr, + bw_def_invalid_linear_or_stereo_mode, + bw_def_invalid_rotation_or_bpp_or_stereo, + bw_def_vsr_mtn_v_taps, + bw_def_vsr_mtn_4, + bw_def_auto, + bw_def_manual, + bw_def_exceeded_allowed_maximum_sclk, + bw_def_exceeded_allowed_page_close_open, + bw_def_exceeded_allowed_outstanding_pte_req_queue_size, + bw_def_exceeded_allowed_maximum_bw, + bw_def_landscape, + + //Panning and bezel + bw_def_any_lines, + + //Underlay mode + bw_def_underlay_only, + bw_def_blended, + bw_def_blend, + + //Stereo mode + bw_def_mono, + bw_def_side_by_side, + bw_def_top_bottom, + + //Underlay surface type + bw_def_420, + bw_def_422, + bw_def_444, + + //Tiling mode + bw_def_linear, + bw_def_tiled, + bw_def_array_linear_general, + bw_def_array_linear_aligned, + bw_def_rotated_micro_tiling, + bw_def_display_micro_tiling, + + //Memory type + bw_def_gddr5, + bw_def_hbm, + + //Voltage + bw_def_high_no_nbp_state_change, + bw_def_0_72, + bw_def_0_8, + bw_def_0_9, + + bw_def_notok = -1, + bw_def_na = -1 +}; + +struct bw_calcs_dceip { + enum bw_calcs_version version; + bool large_cursor; + uint32_t cursor_max_outstanding_group_num; + bool dmif_pipe_en_fbc_chunk_tracker; + struct bw_fixed dmif_request_buffer_size; + uint32_t lines_interleaved_into_lb; + uint32_t low_power_tiling_mode; + uint32_t chunk_width; + uint32_t number_of_graphics_pipes; + uint32_t number_of_underlay_pipes; + bool display_write_back_supported; + bool argb_compression_support; + struct bw_fixed underlay_vscaler_efficiency6_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency8_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency10_bit_per_component; + struct bw_fixed underlay_vscaler_efficiency12_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency6_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency8_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency10_bit_per_component; + struct bw_fixed graphics_vscaler_efficiency12_bit_per_component; + struct bw_fixed alpha_vscaler_efficiency; + uint32_t max_dmif_buffer_allocated; + uint32_t graphics_dmif_size; + uint32_t underlay_luma_dmif_size; + uint32_t underlay_chroma_dmif_size; + bool pre_downscaler_enabled; + bool underlay_downscale_prefetch_enabled; + struct bw_fixed lb_write_pixels_per_dispclk; + struct bw_fixed lb_size_per_component444; + bool graphics_lb_nodownscaling_multi_line_prefetching; + struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor; + struct bw_fixed underlay420_luma_lb_size_per_component; + struct bw_fixed underlay420_chroma_lb_size_per_component; + struct bw_fixed underlay422_lb_size_per_component; + struct bw_fixed cursor_chunk_width; + struct bw_fixed cursor_dcp_buffer_lines; + struct bw_fixed underlay_maximum_width_efficient_for_tiling; + struct bw_fixed underlay_maximum_height_efficient_for_tiling; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation; + struct bw_fixed minimum_outstanding_pte_request_limit; + struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw; + bool limit_excessive_outstanding_dmif_requests; + struct bw_fixed linear_mode_line_request_alternation_slice; + uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode; + uint32_t display_write_back420_luma_mcifwr_buffer_size; + uint32_t display_write_back420_chroma_mcifwr_buffer_size; + struct bw_fixed request_efficiency; + struct bw_fixed dispclk_per_request; + struct bw_fixed dispclk_ramping_factor; + struct bw_fixed display_pipe_throughput_factor; + uint32_t scatter_gather_pte_request_rows_in_tiling_mode; + struct bw_fixed mcifwr_all_surfaces_burst_time; +}; + +struct bw_calcs_vbios { + enum bw_defines memory_type; + uint32_t dram_channel_width_in_bits; + uint32_t number_of_dram_channels; + uint32_t number_of_dram_banks; + struct bw_fixed low_yclk; /*m_hz*/ + struct bw_fixed mid_yclk; /*m_hz*/ + struct bw_fixed high_yclk; /*m_hz*/ + struct bw_fixed low_sclk; /*m_hz*/ + struct bw_fixed mid1_sclk; /*m_hz*/ + struct bw_fixed mid2_sclk; /*m_hz*/ + struct bw_fixed mid3_sclk; /*m_hz*/ + struct bw_fixed mid4_sclk; /*m_hz*/ + struct bw_fixed mid5_sclk; /*m_hz*/ + struct bw_fixed mid6_sclk; /*m_hz*/ + struct bw_fixed high_sclk; /*m_hz*/ + struct bw_fixed low_voltage_max_dispclk; /*m_hz*/ + struct bw_fixed mid_voltage_max_dispclk; /*m_hz*/ + struct bw_fixed high_voltage_max_dispclk; /*m_hz*/ + struct bw_fixed low_voltage_max_phyclk; + struct bw_fixed mid_voltage_max_phyclk; + struct bw_fixed high_voltage_max_phyclk; + struct bw_fixed data_return_bus_width; + struct bw_fixed trc; + struct bw_fixed dmifmc_urgent_latency; + struct bw_fixed stutter_self_refresh_exit_latency; + struct bw_fixed stutter_self_refresh_entry_latency; + struct bw_fixed nbp_state_change_latency; + struct bw_fixed mcifwrmc_urgent_latency; + bool scatter_gather_enable; + struct bw_fixed down_spread_percentage; + uint32_t cursor_width; + uint32_t average_compression_rate; + uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel; + struct bw_fixed blackout_duration; + struct bw_fixed maximum_blackout_recovery_time; +}; + +/******************************************************************************* + * Temporary data structure(s). + ******************************************************************************/ +#define maximum_number_of_surfaces 12 +/*Units : MHz, us */ + +struct bw_calcs_data { + /* data for all displays */ + uint32_t number_of_displays; + enum bw_defines underlay_surface_type; + enum bw_defines panning_and_bezel_adjustment; + enum bw_defines graphics_tiling_mode; + uint32_t graphics_lb_bpc; + uint32_t underlay_lb_bpc; + enum bw_defines underlay_tiling_mode; + enum bw_defines d0_underlay_mode; + bool d1_display_write_back_dwb_enable; + enum bw_defines d1_underlay_mode; + + bool cpup_state_change_enable; + bool cpuc_state_change_enable; + bool nbp_state_change_enable; + bool stutter_mode_enable; + uint32_t y_clk_level; + uint32_t sclk_level; + uint32_t number_of_underlay_surfaces; + uint32_t number_of_dram_wrchannels; + uint32_t chunk_request_delay; + uint32_t number_of_dram_channels; + enum bw_defines underlay_micro_tile_mode; + enum bw_defines graphics_micro_tile_mode; + struct bw_fixed max_phyclk; + struct bw_fixed dram_efficiency; + struct bw_fixed src_width_after_surface_type; + struct bw_fixed src_height_after_surface_type; + struct bw_fixed hsr_after_surface_type; + struct bw_fixed vsr_after_surface_type; + struct bw_fixed src_width_after_rotation; + struct bw_fixed src_height_after_rotation; + struct bw_fixed hsr_after_rotation; + struct bw_fixed vsr_after_rotation; + struct bw_fixed source_height_pixels; + struct bw_fixed hsr_after_stereo; + struct bw_fixed vsr_after_stereo; + struct bw_fixed source_width_in_lb; + struct bw_fixed lb_line_pitch; + struct bw_fixed underlay_maximum_source_efficient_for_tiling; + struct bw_fixed num_lines_at_frame_start; + struct bw_fixed min_dmif_size_in_time; + struct bw_fixed min_mcifwr_size_in_time; + struct bw_fixed total_requests_for_dmif_size; + struct bw_fixed peak_pte_request_to_eviction_ratio_limiting; + struct bw_fixed useful_pte_per_pte_request; + struct bw_fixed scatter_gather_pte_request_rows; + struct bw_fixed scatter_gather_row_height; + struct bw_fixed scatter_gather_pte_requests_in_vblank; + struct bw_fixed inefficient_linear_pitch_in_bytes; + struct bw_fixed cursor_total_data; + struct bw_fixed cursor_total_request_groups; + struct bw_fixed scatter_gather_total_pte_requests; + struct bw_fixed scatter_gather_total_pte_request_groups; + struct bw_fixed tile_width_in_pixels; + struct bw_fixed dmif_total_number_of_data_request_page_close_open; + struct bw_fixed mcifwr_total_number_of_data_request_page_close_open; + struct bw_fixed bytes_per_page_close_open; + struct bw_fixed mcifwr_total_page_close_open_time; + struct bw_fixed total_requests_for_adjusted_dmif_size; + struct bw_fixed total_dmifmc_urgent_trips; + struct bw_fixed total_dmifmc_urgent_latency; + struct bw_fixed total_display_reads_required_data; + struct bw_fixed total_display_reads_required_dram_access_data; + struct bw_fixed total_display_writes_required_data; + struct bw_fixed total_display_writes_required_dram_access_data; + struct bw_fixed display_reads_required_data; + struct bw_fixed display_reads_required_dram_access_data; + struct bw_fixed dmif_total_page_close_open_time; + struct bw_fixed min_cursor_memory_interface_buffer_size_in_time; + struct bw_fixed min_read_buffer_size_in_time; + struct bw_fixed display_reads_time_for_data_transfer; + struct bw_fixed display_writes_time_for_data_transfer; + struct bw_fixed dmif_required_dram_bandwidth; + struct bw_fixed mcifwr_required_dram_bandwidth; + struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open; + struct bw_fixed required_mcifmcwr_urgent_latency; + struct bw_fixed required_dram_bandwidth_gbyte_per_second; + struct bw_fixed dram_bandwidth; + struct bw_fixed dmif_required_sclk; + struct bw_fixed mcifwr_required_sclk; + struct bw_fixed required_sclk; + struct bw_fixed downspread_factor; + struct bw_fixed v_scaler_efficiency; + struct bw_fixed scaler_limits_factor; + struct bw_fixed display_pipe_pixel_throughput; + struct bw_fixed total_dispclk_required_with_ramping; + struct bw_fixed total_dispclk_required_without_ramping; + struct bw_fixed total_read_request_bandwidth; + struct bw_fixed total_write_request_bandwidth; + struct bw_fixed dispclk_required_for_total_read_request_bandwidth; + struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth; + struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth; + struct bw_fixed dispclk; + struct bw_fixed blackout_recovery_time; + struct bw_fixed min_pixels_per_data_fifo_entry; + struct bw_fixed sclk_deep_sleep; + struct bw_fixed chunk_request_time; + struct bw_fixed cursor_request_time; + struct bw_fixed line_source_pixels_transfer_time; + struct bw_fixed dmifdram_access_efficiency; + struct bw_fixed mcifwrdram_access_efficiency; + struct bw_fixed total_average_bandwidth_no_compression; + struct bw_fixed total_average_bandwidth; + struct bw_fixed total_stutter_cycle_duration; + struct bw_fixed stutter_burst_time; + struct bw_fixed time_in_self_refresh; + struct bw_fixed stutter_efficiency; + struct bw_fixed worst_number_of_trips_to_memory; + struct bw_fixed immediate_flip_time; + struct bw_fixed latency_for_non_dmif_clients; + struct bw_fixed latency_for_non_mcifwr_clients; + struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk; + struct bw_fixed nbp_state_dram_speed_change_margin; + struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency; + struct bw_fixed dram_speed_change_margin; + struct bw_fixed min_vblank_dram_speed_change_margin; + struct bw_fixed min_stutter_refresh_duration; + uint32_t total_stutter_dmif_buffer_size; + uint32_t total_bytes_requested; + uint32_t min_stutter_dmif_buffer_size; + uint32_t num_stutter_bursts; + struct bw_fixed v_blank_nbp_state_dram_speed_change_latency_supported; + struct bw_fixed nbp_state_dram_speed_change_latency_supported; + bool fbc_en[maximum_number_of_surfaces]; + bool lpt_en[maximum_number_of_surfaces]; + bool displays_match_flag[maximum_number_of_surfaces]; + bool use_alpha[maximum_number_of_surfaces]; + bool orthogonal_rotation[maximum_number_of_surfaces]; + bool enable[maximum_number_of_surfaces]; + bool access_one_channel_only[maximum_number_of_surfaces]; + bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces]; + bool interlace_mode[maximum_number_of_surfaces]; + bool display_pstate_change_enable[maximum_number_of_surfaces]; + bool line_buffer_prefetch[maximum_number_of_surfaces]; + uint32_t bytes_per_pixel[maximum_number_of_surfaces]; + uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces]; + uint32_t lb_bpc[maximum_number_of_surfaces]; + uint32_t output_bpphdmi[maximum_number_of_surfaces]; + uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces]; + uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces]; + uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces]; + enum bw_defines stereo_mode[maximum_number_of_surfaces]; + struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces]; + struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces]; + struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces]; + struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces]; + struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces]; + struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces]; + struct bw_fixed h_total[maximum_number_of_surfaces]; + struct bw_fixed v_total[maximum_number_of_surfaces]; + struct bw_fixed pixel_rate[maximum_number_of_surfaces]; + struct bw_fixed src_width[maximum_number_of_surfaces]; + struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces]; + struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces]; + struct bw_fixed src_height[maximum_number_of_surfaces]; + struct bw_fixed scale_ratio[maximum_number_of_surfaces]; + struct bw_fixed h_taps[maximum_number_of_surfaces]; + struct bw_fixed v_taps[maximum_number_of_surfaces]; + struct bw_fixed h_scale_ratio[maximum_number_of_surfaces]; + struct bw_fixed v_scale_ratio[maximum_number_of_surfaces]; + struct bw_fixed rotation_angle[maximum_number_of_surfaces]; + struct bw_fixed compression_rate[maximum_number_of_surfaces]; + struct bw_fixed hsr[maximum_number_of_surfaces]; + struct bw_fixed vsr[maximum_number_of_surfaces]; + struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces]; + struct bw_fixed source_width_pixels[maximum_number_of_surfaces]; + struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces]; + struct bw_fixed display_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed request_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed bytes_per_request[maximum_number_of_surfaces]; + struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces]; + struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces]; + struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces]; + struct bw_fixed lb_partitions[maximum_number_of_surfaces]; + struct bw_fixed lb_partitions_max[maximum_number_of_surfaces]; + struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces]; + struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces]; + struct bw_fixed data_buffer_size[maximum_number_of_surfaces]; + struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces]; + struct bw_fixed urgent_watermark[maximum_number_of_surfaces]; + struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces]; + struct bw_fixed v_filter_init[maximum_number_of_surfaces]; + struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces]; + struct bw_fixed average_bandwidth[maximum_number_of_surfaces]; + struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces]; + struct bw_fixed lb_size_per_component[maximum_number_of_surfaces]; + struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces]; + struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces]; + struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces]; + struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces]; + struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces]; + struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces]; + struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces]; + struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces]; + struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces]; + struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces]; + struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces]; + struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces]; + struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces]; + struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces]; + struct bw_fixed active_time[maximum_number_of_surfaces]; + struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces]; + struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces]; + struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces]; + uint32_t num_displays_with_margin[3][8]; + struct bw_fixed dmif_burst_time[3][8]; + struct bw_fixed mcifwr_burst_time[3][8]; + struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8]; + struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8]; + struct bw_fixed min_dram_speed_change_margin[3][8]; + struct bw_fixed dispclk_required_for_dram_speed_change[3][8]; + struct bw_fixed blackout_duration_margin[3][8]; + struct bw_fixed dispclk_required_for_blackout_duration[3][8]; + struct bw_fixed dispclk_required_for_blackout_recovery[3][8]; + struct bw_fixed dmif_required_sclk_for_urgent_latency[6]; +}; + +/******************************************************************************* + * Output data structures. + ******************************************************************************/ +struct bw_watermarks { + uint32_t a_mark; + uint32_t b_mark; + uint32_t c_mark; + uint32_t d_mark; +}; + +struct bw_calcs_output { + bool cpuc_state_change_enable; + bool cpup_state_change_enable; + bool stutter_mode_enable; + bool nbp_state_change_enable; + bool all_displays_in_sync; + struct bw_watermarks urgent_wm_ns[6]; + struct bw_watermarks stutter_exit_wm_ns[6]; + struct bw_watermarks nbp_state_change_wm_ns[6]; + uint32_t required_sclk; + uint32_t required_sclk_deep_sleep; + uint32_t required_yclk; + uint32_t dispclk_khz; + int blackout_recovery_time_us; +}; + +/** + * Initialize structures with data which will NOT change at runtime. + */ +void bw_calcs_init( + struct bw_calcs_dceip *bw_dceip, + struct bw_calcs_vbios *bw_vbios, + enum bw_calcs_version version); + +/** + * Return: + * true - Display(s) configuration supported. + * In this case 'calcs_output' contains data for HW programming + * false - Display(s) configuration not supported (not enough bandwidth). + */ +bool bw_calcs( + struct dc_context *ctx, + const struct bw_calcs_dceip *dceip, + const struct bw_calcs_vbios *vbios, + const struct pipe_ctx *pipe, + int pipe_count, + struct bw_calcs_output *calcs_output); + +#endif /* __BANDWIDTH_CALCS_H__ */ + diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h new file mode 100644 index 000000000000..b31d07a57c31 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h @@ -0,0 +1,63 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef BW_FIXED_H_ +#define BW_FIXED_H_ + +struct bw_fixed { + int64_t value; +}; + +struct bw_fixed bw_min3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3); + +struct bw_fixed bw_max3(struct bw_fixed v1, struct bw_fixed v2, struct bw_fixed v3); + +struct bw_fixed bw_int_to_fixed(int64_t value); + +int32_t bw_fixed_to_int(struct bw_fixed value); + +struct bw_fixed bw_frc_to_fixed(int64_t num, int64_t denum); + +struct bw_fixed fixed31_32_to_bw_fixed(int64_t raw); + +struct bw_fixed bw_add(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_sub(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_mul(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_div(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_mod(const struct bw_fixed arg1, const struct bw_fixed arg2); + +struct bw_fixed bw_min2(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_max2(const struct bw_fixed arg1, const struct bw_fixed arg2); +struct bw_fixed bw_floor2(const struct bw_fixed arg, const struct bw_fixed significance); +struct bw_fixed bw_ceil2(const struct bw_fixed arg, const struct bw_fixed significance); + +bool bw_equ(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_neq(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_leq(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_meq(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_ltn(const struct bw_fixed arg1, const struct bw_fixed arg2); +bool bw_mtn(const struct bw_fixed arg1, const struct bw_fixed arg2); + +#endif //BW_FIXED_H_ diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h new file mode 100644 index 000000000000..c91c7815ec6e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h @@ -0,0 +1,178 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_CLOCK_SOURCE_H__ +#define __DC_CLOCK_SOURCE_H__ + +#include "dc_types.h" +#include "include/grph_object_id.h" +#include "include/bios_parser_types.h" + +struct clock_source; + +struct spread_spectrum_data { + uint32_t percentage; /*> In unit of 0.01% or 0.001%*/ + uint32_t percentage_divider; /*> 100 or 1000 */ + uint32_t freq_range_khz; + uint32_t modulation_freq_hz; + + struct spread_spectrum_flags flags; +}; + +struct delta_sigma_data { + uint32_t feedback_amount; + uint32_t nfrac_amount; + uint32_t ds_frac_size; + uint32_t ds_frac_amount; +}; + +/** + * Pixel Clock Parameters structure + * These parameters are required as input + * when calculating Pixel Clock Dividers for requested Pixel Clock + */ +struct pixel_clk_flags { + uint32_t ENABLE_SS:1; + uint32_t DISPLAY_BLANKED:1; + uint32_t PROGRAM_PIXEL_CLOCK:1; + uint32_t PROGRAM_ID_CLOCK:1; + uint32_t SUPPORT_YCBCR420:1; +}; + +/** + * Display Port HW De spread of Reference Clock related Parameters structure + * Store it once at boot for later usage + */ +struct csdp_ref_clk_ds_params { + bool hw_dso_n_dp_ref_clk; +/* Flag for HW De Spread enabled (if enabled SS on DP Reference Clock)*/ + uint32_t avg_dp_ref_clk_khz; +/* Average DP Reference clock (in KHz)*/ + uint32_t ss_percentage_on_dp_ref_clk; +/* DP Reference clock SS percentage + * (not to be mixed with DP IDCLK SS from PLL Settings)*/ + uint32_t ss_percentage_divider; +/* DP Reference clock SS percentage divider */ +}; + +struct pixel_clk_params { + uint32_t requested_pix_clk; /* in KHz */ +/*> Requested Pixel Clock + * (based on Video Timing standard used for requested mode)*/ + uint32_t requested_sym_clk; /* in KHz */ +/*> Requested Sym Clock (relevant only for display port)*/ + uint32_t dp_ref_clk; /* in KHz */ +/*> DP reference clock - calculated only for DP signal for specific cases*/ + struct graphics_object_id encoder_object_id; +/*> Encoder object Id - needed by VBIOS Exec table*/ + enum signal_type signal_type; +/*> signalType -> Encoder Mode - needed by VBIOS Exec table*/ + enum controller_id controller_id; +/*> ControllerId - which controller using this PLL*/ + enum dc_color_depth color_depth; + struct csdp_ref_clk_ds_params de_spread_params; +/*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/ + + struct pixel_clk_flags flags; +}; + +/** + * Pixel Clock Dividers structure with desired Pixel Clock + * (adjusted after VBIOS exec table), + * with actually calculated Clock and reference Crystal frequency + */ +struct pll_settings { + uint32_t actual_pix_clk; + uint32_t adjusted_pix_clk; + uint32_t calculated_pix_clk; + uint32_t vco_freq; + uint32_t reference_freq; + uint32_t reference_divider; + uint32_t feedback_divider; + uint32_t fract_feedback_divider; + uint32_t pix_clk_post_divider; + uint32_t ss_percentage; + bool use_external_clk; +}; + +struct calc_pll_clock_source_init_data { + struct dc_bios *bp; + uint32_t min_pix_clk_pll_post_divider; + uint32_t max_pix_clk_pll_post_divider; + uint32_t min_pll_ref_divider; + uint32_t max_pll_ref_divider; + uint32_t min_override_input_pxl_clk_pll_freq_khz; +/* if not 0, override the firmware info */ + + uint32_t max_override_input_pxl_clk_pll_freq_khz; +/* if not 0, override the firmware info */ + + uint32_t num_fract_fb_divider_decimal_point; +/* number of decimal point for fractional feedback divider value */ + + uint32_t num_fract_fb_divider_decimal_point_precision; +/* number of decimal point to round off for fractional feedback divider value*/ + struct dc_context *ctx; + +}; + +struct calc_pll_clock_source { + uint32_t ref_freq_khz; + uint32_t min_pix_clock_pll_post_divider; + uint32_t max_pix_clock_pll_post_divider; + uint32_t min_pll_ref_divider; + uint32_t max_pll_ref_divider; + + uint32_t max_vco_khz; + uint32_t min_vco_khz; + uint32_t min_pll_input_freq_khz; + uint32_t max_pll_input_freq_khz; + + uint32_t fract_fb_divider_decimal_points_num; + uint32_t fract_fb_divider_factor; + uint32_t fract_fb_divider_precision; + uint32_t fract_fb_divider_precision_factor; + struct dc_context *ctx; +}; + +struct clock_source_funcs { + bool (*cs_power_down)( + struct clock_source *); + bool (*program_pix_clk)(struct clock_source *, + struct pixel_clk_params *, struct pll_settings *); + uint32_t (*get_pix_clk_dividers)( + struct clock_source *, + struct pixel_clk_params *, + struct pll_settings *); +}; + +struct clock_source { + const struct clock_source_funcs *funcs; + struct dc_context *ctx; + enum clock_source_id id; + bool dp_clk_src; +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/compressor.h b/drivers/gpu/drm/amd/display/dc/inc/compressor.h new file mode 100644 index 000000000000..af292596b101 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/compressor.h @@ -0,0 +1,93 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_COMPRESSOR_H__ +#define __DAL_COMPRESSOR_H__ + +#include "include/grph_object_id.h" +#include "bios_parser_interface.h" + +enum fbc_compress_ratio { + FBC_COMPRESS_RATIO_INVALID = 0, + FBC_COMPRESS_RATIO_1TO1 = 1, + FBC_COMPRESS_RATIO_2TO1 = 2, + FBC_COMPRESS_RATIO_4TO1 = 4, + FBC_COMPRESS_RATIO_8TO1 = 8, +}; + +union fbc_physical_address { + struct { + uint32_t low_part; + int32_t high_part; + } addr; +}; + +struct compr_addr_and_pitch_params { + uint32_t inst; + uint32_t source_view_width; + uint32_t source_view_height; +}; + +enum fbc_hw_max_resolution_supported { + FBC_MAX_X = 3840, + FBC_MAX_Y = 2400 +}; + +struct compressor { + struct dc_context *ctx; + uint32_t attached_inst; + bool is_enabled; + + union { + uint32_t raw; + struct { + uint32_t FBC_SUPPORT:1; + uint32_t FB_POOL:1; + uint32_t DYNAMIC_ALLOC:1; + uint32_t LPT_SUPPORT:1; + uint32_t LPT_MC_CONFIG:1; + uint32_t DUMMY_BACKEND:1; + uint32_t CLK_GATING_DISABLED:1; + + } bits; + } options; + + union fbc_physical_address compr_surface_address; + + uint32_t embedded_panel_h_size; + uint32_t embedded_panel_v_size; + uint32_t memory_bus_width; + uint32_t banks_num; + uint32_t raw_size; + uint32_t channel_interleave_size; + uint32_t dram_channels_num; + + uint32_t allocated_size; + uint32_t preferred_requested_size; + uint32_t lpt_channels_num; + enum fbc_compress_ratio min_compress_ratio; +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h new file mode 100644 index 000000000000..7d6dc8ea75ab --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -0,0 +1,50 @@ +/* + * core_dc.h + * + * Created on: Nov 13, 2015 + * Author: yonsun + */ + +#ifndef __CORE_DC_H__ +#define __CORE_DC_H__ + +#include "core_types.h" +#include "hw_sequencer.h" + +#define DC_TO_CORE(dc)\ + container_of(dc, struct core_dc, public) + +struct core_dc { + struct dc public; + struct dc_context *ctx; + + uint8_t link_count; + struct core_link *links[MAX_PIPES * 2]; + + /* TODO: determine max number of targets*/ + struct validate_context *current_context; + struct validate_context *temp_flip_context; + struct resource_pool *res_pool; + + /*Power State*/ + enum dc_video_power_state previous_power_state; + enum dc_video_power_state current_power_state; + + /* Display Engine Clock levels */ + struct dm_pp_clock_levels sclk_lvls; + + /* Inputs into BW and WM calculations. */ + struct bw_calcs_dceip bw_dceip; + struct bw_calcs_vbios bw_vbios; + + /* HW functions */ + struct hw_sequencer_funcs hwss; + struct dce_hwseq *hwseq; + + /* temp store of dm_pp_display_configuration + * to compare to see if display config changed + */ + struct dm_pp_display_configuration prev_display_config; +}; + +#endif /* __CORE_DC_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h new file mode 100644 index 000000000000..32a2cc712000 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h @@ -0,0 +1,47 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _CORE_STATUS_H_ +#define _CORE_STATUS_H_ + +enum dc_status { + DC_OK = 1, + + DC_NO_CONTROLLER_RESOURCE, + DC_NO_STREAM_ENG_RESOURCE, + DC_NO_CLOCK_SOURCE_RESOURCE, + DC_FAIL_CONTROLLER_VALIDATE, + DC_FAIL_ENC_VALIDATE, + DC_FAIL_ATTACH_SURFACES, + DC_FAIL_SURFACE_VALIDATE, + DC_NO_DP_LINK_BANDWIDTH, + DC_EXCEED_DONGLE_MAX_CLK, + DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED, + DC_FAIL_BANDWIDTH_VALIDATE, /* BW and Watermark validation */ + + DC_ERROR_UNEXPECTED = -1 +}; + +#endif /* _CORE_STATUS_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h new file mode 100644 index 000000000000..f2eb8945d5c4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -0,0 +1,319 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _CORE_TYPES_H_ +#define _CORE_TYPES_H_ + +#include "dc.h" +#include "bandwidth_calcs.h" +#include "ddc_service_types.h" +#include "dc_bios_types.h" + +struct core_stream; +/********* core_target *************/ + +#define CONST_DC_TARGET_TO_CORE(dc_target) \ + container_of(dc_target, const struct core_target, public) +#define DC_TARGET_TO_CORE(dc_target) \ + container_of(dc_target, struct core_target, public) + +#define MAX_PIPES 6 +#define MAX_CLOCK_SOURCES 7 + +struct core_target { + struct dc_target public; + + struct dc_context *ctx; +}; + +/********* core_surface **********/ +#define DC_SURFACE_TO_CORE(dc_surface) \ + container_of(dc_surface, struct core_surface, public) + +#define DC_GAMMA_TO_CORE(dc_gamma) \ + container_of(dc_gamma, struct core_gamma, public) + +struct core_surface { + struct dc_surface public; + struct dc_surface_status status; + struct dc_context *ctx; +}; + +struct core_gamma { + struct dc_gamma public; + struct dc_context *ctx; +}; + +void enable_surface_flip_reporting(struct dc_surface *dc_surface, + uint32_t controller_id); + +/********* core_stream ************/ +#include "grph_object_id.h" +#include "link_encoder.h" +#include "stream_encoder.h" +#include "clock_source.h" +#include "audio.h" +#include "hw_sequencer_types.h" +#include "opp.h" + +#define DC_STREAM_TO_CORE(dc_stream) container_of( \ + dc_stream, struct core_stream, public) + +struct core_stream { + struct dc_stream public; + + /* field internal to DC */ + struct dc_context *ctx; + const struct core_sink *sink; + + /* used by DCP and FMT */ + struct bit_depth_reduction_params bit_depth_params; + struct clamping_and_pixel_encoding_params clamping; + + int phy_pix_clk; + enum signal_type signal; + + struct dc_stream_status status; +}; + +/************ core_sink *****************/ + +#define DC_SINK_TO_CORE(dc_sink) \ + container_of(dc_sink, struct core_sink, public) + +struct core_sink { + /** The public, read-only (for DM) area of sink. **/ + struct dc_sink public; + /** End-of-public area. **/ + + /** The 'protected' area - read/write access, for use only inside DC **/ + /* not used for now */ + struct core_link *link; + struct dc_context *ctx; + uint32_t dongle_max_pix_clk; + bool converter_disable_audio; +}; + +/************ link *****************/ +#define DC_LINK_TO_CORE(dc_link) container_of(dc_link, struct core_link, public) + +struct link_init_data { + const struct core_dc *dc; + struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ + uint32_t connector_index; /* this will be mapped to the HPD pins */ + uint32_t link_index; /* this is mapped to DAL display_index + TODO: remove it when DC is complete. */ +}; + +/* DP MST stream allocation (payload bandwidth number) */ +struct link_mst_stream_allocation { + /* DIG front */ + const struct stream_encoder *stream_enc; + /* associate DRM payload table with DC stream encoder */ + uint8_t vcp_id; + /* number of slots required for the DP stream in transport packet */ + uint8_t slot_count; +}; + +/* DP MST stream allocation table */ +struct link_mst_stream_allocation_table { + /* number of DP video streams */ + int stream_count; + /* array of stream allocations */ + struct link_mst_stream_allocation + stream_allocations[MAX_CONTROLLER_NUM]; +}; + +struct core_link { + struct dc_link public; + const struct core_dc *dc; + + struct dc_context *ctx; /* TODO: AUTO remove 'dal' when DC is complete*/ + + struct link_encoder *link_enc; + struct ddc_service *ddc; + struct graphics_object_id link_id; + union ddi_channel_mapping ddi_channel_mapping; + struct connector_device_tag_info device_tag; + struct dpcd_caps dpcd_caps; + unsigned int dpcd_sink_count; + + enum edp_revision edp_revision; + + /* MST record stream using this link */ + struct link_flags { + bool dp_keep_receiver_powered; + } wa_flags; + struct link_mst_stream_allocation_table mst_stream_alloc_table; + + struct dc_link_status link_status; +}; + +#define DC_LINK_TO_LINK(dc_link) container_of(dc_link, struct core_link, public) + +struct core_link *link_create(const struct link_init_data *init_params); +void link_destroy(struct core_link **link); + +enum dc_status dc_link_validate_mode_timing( + const struct core_stream *stream, + struct core_link *link, + const struct dc_crtc_timing *timing); + +void core_link_resume(struct core_link *link); + +void core_link_enable_stream(struct pipe_ctx *pipe_ctx); + +void core_link_disable_stream(struct pipe_ctx *pipe_ctx); + +/********** DAL Core*********************/ +#include "display_clock_interface.h" +#include "transform.h" + +struct resource_pool; +struct validate_context; +struct resource_context; + +struct resource_funcs { + void (*destroy)(struct resource_pool **pool); + struct link_encoder *(*link_enc_create)( + const struct encoder_init_data *init); + enum dc_status (*validate_with_context)( + const struct core_dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *context); + + enum dc_status (*validate_guaranteed)( + const struct core_dc *dc, + const struct dc_target *dc_target, + struct validate_context *context); + + enum dc_status (*validate_bandwidth)( + const struct core_dc *dc, + struct validate_context *context); + + struct validate_context *(*apply_clk_constraints)( + const struct core_dc *dc, + struct validate_context *context); + + struct pipe_ctx *(*acquire_idle_pipe_for_layer)( + struct resource_context *res_ctx, + struct core_stream *stream); + + void (*build_bit_depth_reduction_params)( + const struct core_stream *stream, + struct bit_depth_reduction_params *fmt_bit_depth); +}; + +struct audio_support{ + bool dp_audio; + bool hdmi_audio_on_dongle; + bool hdmi_audio_native; +}; + +struct resource_pool { + struct mem_input *mis[MAX_PIPES]; + struct input_pixel_processor *ipps[MAX_PIPES]; + struct transform *transforms[MAX_PIPES]; + struct output_pixel_processor *opps[MAX_PIPES]; + struct timing_generator *timing_generators[MAX_PIPES]; + struct stream_encoder *stream_enc[MAX_PIPES * 2]; + + unsigned int pipe_count; + unsigned int underlay_pipe_index; + unsigned int stream_enc_count; + + /* + * reserved clock source for DP + */ + struct clock_source *dp_clock_source; + + struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; + unsigned int clk_src_count; + + struct audio *audios[MAX_PIPES]; + unsigned int audio_count; + struct audio_support audio_support; + + struct display_clock *display_clock; + struct irq_service *irqs; + + const struct resource_funcs *funcs; + const struct resource_caps *res_cap; +}; + +struct pipe_ctx { + struct core_surface *surface; + struct core_stream *stream; + + struct mem_input *mi; + struct input_pixel_processor *ipp; + struct transform *xfm; + struct output_pixel_processor *opp; + struct timing_generator *tg; + + struct scaler_data scl_data; + + struct stream_encoder *stream_enc; + struct display_clock *dis_clk; + struct clock_source *clock_source; + + struct audio *audio; + + struct pixel_clk_params pix_clk_params; + struct pll_settings pll_settings; + + /*fmt*/ + struct encoder_info_frame encoder_info_frame; + + uint8_t pipe_idx; + + struct pipe_ctx *top_pipe; + struct pipe_ctx *bottom_pipe; +}; + +struct resource_context { + const struct resource_pool *pool; + struct pipe_ctx pipe_ctx[MAX_PIPES]; + bool is_stream_enc_acquired[MAX_PIPES * 2]; + bool is_audio_acquired[MAX_PIPES]; + uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; + uint8_t dp_clock_source_ref_count; + }; + +struct validate_context { + struct core_target *targets[MAX_PIPES]; + struct dc_target_status target_status[MAX_PIPES]; + uint8_t target_count; + + struct resource_context res_ctx; + + /* The output from BW and WM calculations. */ + struct bw_calcs_output bw_results; + /* Note: this is a big structure, do *not* put on stack! */ + struct dm_pp_display_configuration pp_display_cfg; +}; + +#endif /* _CORE_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h new file mode 100644 index 000000000000..830fc3d039c9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h @@ -0,0 +1,145 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_DDC_SERVICE_H__ +#define __DAL_DDC_SERVICE_H__ + +#include "include/ddc_service_types.h" +#include "include/i2caux_interface.h" + +#define EDID_SEGMENT_SIZE 256 + +struct ddc_service; +struct graphics_object_id; +enum ddc_result; +struct av_sync_data; +struct dp_receiver_id_info; + +struct i2c_payloads; +struct aux_payloads; + +struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_t count); +struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p); +uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p); +void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p); + +struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_t count); +struct aux_payload *dal_ddc_aux_payloads_get(struct aux_payloads *p); +uint32_t dal_ddc_aux_payloads_get_count(struct aux_payloads *p); +void dal_ddc_aux_payloads_destroy(struct aux_payloads **p); + +void dal_ddc_i2c_payloads_add( + struct i2c_payloads *payloads, + uint32_t address, + uint32_t len, + uint8_t *data, + bool write); + +void dal_ddc_aux_payloads_add( + struct aux_payloads *payloads, + uint32_t address, + uint32_t len, + uint8_t *data, + bool write); + +struct ddc_service_init_data { + struct graphics_object_id id; + struct dc_context *ctx; + struct core_link *link; +}; + +struct ddc_service *dal_ddc_service_create( + struct ddc_service_init_data *ddc_init_data); + +void dal_ddc_service_destroy(struct ddc_service **ddc); + +enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc); + +void dal_ddc_service_set_transaction_type( + struct ddc_service *ddc, + enum ddc_transaction_type type); + +bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc); + +uint32_t dal_ddc_service_edid_query(struct ddc_service *ddc); + +uint32_t dal_ddc_service_get_edid_buf_len(struct ddc_service *ddc); + +void dal_ddc_service_get_edid_buf(struct ddc_service *ddc, uint8_t *edid_buf); + +void dal_ddc_service_i2c_query_dp_dual_mode_adaptor( + struct ddc_service *ddc, + struct display_sink_capability *sink_cap); + +bool dal_ddc_service_query_ddc_data( + struct ddc_service *ddc, + uint32_t address, + uint8_t *write_buf, + uint32_t write_size, + uint8_t *read_buf, + uint32_t read_size); + +enum ddc_result dal_ddc_service_read_dpcd_data( + struct ddc_service *ddc, + uint32_t address, + uint8_t *data, + uint32_t len); + +enum ddc_result dal_ddc_service_write_dpcd_data( + struct ddc_service *ddc, + uint32_t address, + const uint8_t *data, + uint32_t len); + +void dal_ddc_service_write_scdc_data( + struct ddc_service *ddc_service, + uint32_t pix_clk, + bool lte_340_scramble); + +void dal_ddc_service_read_scdc_data( + struct ddc_service *ddc_service); + +void ddc_service_set_dongle_type(struct ddc_service *ddc, + enum display_dongle_type dongle_type); + +void dal_ddc_service_set_ddc_pin( + struct ddc_service *ddc_service, + struct ddc *ddc); + +struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service); + +enum ddc_result dal_ddc_service_read_dpcd_data( + struct ddc_service *ddc, + uint32_t address, + uint8_t *data, + uint32_t len); +enum ddc_result dal_ddc_service_write_dpcd_data( + struct ddc_service *ddc, + uint32_t address, + const uint8_t *data, + uint32_t len); + +#endif /* __DAL_DDC_SERVICE_H__ */ + diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h new file mode 100644 index 000000000000..b0cf8e00059c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -0,0 +1,60 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_LINK_DP_H__ +#define __DC_LINK_DP_H__ + +#define LINK_TRAINING_ATTEMPTS 4 +#define LINK_TRAINING_RETRY_DELAY 50 /* ms */ + +struct core_link; +struct core_stream; +struct dc_link_settings; + +bool dp_hbr_verify_link_cap( + struct core_link *link, + struct dc_link_settings *known_limit_link_setting); + +bool dp_validate_mode_timing( + struct core_link *link, + const struct dc_crtc_timing *timing); + +void decide_link_settings( + struct core_stream *stream, + struct dc_link_settings *link_setting); + +bool perform_link_training_with_retries( + struct core_link *link, + const struct dc_link_settings *link_setting, + bool skip_video_pattern, + int attempts); + +bool is_mst_supported(struct core_link *link); + +void detect_dp_sink_caps(struct core_link *link); + +bool is_dp_active_dongle(const struct core_link *link); + +#endif /* __DC_LINK_DP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h new file mode 100644 index 000000000000..e2c63fd4fe92 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/gamma_calcs.h @@ -0,0 +1,19 @@ +/* + * gamma_calcs.h + * + * Created on: Feb 9, 2016 + * Author: yonsun + */ + +#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_ +#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_ + +#include "opp.h" +#include "core_types.h" +#include "dc.h" + +bool calculate_regamma_params(struct pwl_params *params, + const struct core_gamma *ramp, + const struct core_surface *surface); + +#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_GAMMA_CALCS_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/gamma_types.h b/drivers/gpu/drm/amd/display/dc/inc/gamma_types.h new file mode 100644 index 000000000000..7948d2cc0715 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/gamma_types.h @@ -0,0 +1,38 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef GAMMA_TYPES_H_ + +#define GAMMA_TYPES_H_ + +#include "dc_types.h" + +/* TODO: Used in IPP and OPP */ + +struct dev_c_lut16 { + uint16_t red; + uint16_t green; + uint16_t blue; +}; +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h b/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h new file mode 100644 index 000000000000..925204f49717 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/audio.h @@ -0,0 +1,62 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_AUDIO_H__ +#define __DAL_AUDIO_H__ + +#include "audio_types.h" + +struct audio; + +struct audio_funcs { + + bool (*endpoint_valid)(struct audio *audio); + + void (*hw_init)(struct audio *audio); + + void (*az_enable)(struct audio *audio); + + void (*az_disable)(struct audio *audio); + + void (*az_configure)(struct audio *audio, + enum signal_type signal, + const struct audio_crtc_info *crtc_info, + const struct audio_info *audio_info); + + void (*wall_dto_setup)(struct audio *audio, + enum signal_type signal, + const struct audio_crtc_info *crtc_info, + const struct audio_pll_info *pll_info); + + void (*destroy)(struct audio **audio); +}; + +struct audio { + const struct audio_funcs *funcs; + struct dc_context *ctx; + unsigned int inst; +}; + +#endif /* __DAL_AUDIO__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h b/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h new file mode 100644 index 000000000000..90d0148430fb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/gpio.h @@ -0,0 +1,86 @@ +/* + * Copyright 2012-16 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_GPIO_H__ +#define __DAL_GPIO_H__ + +#include "gpio_types.h" + +struct gpio { + struct gpio_service *service; + struct hw_gpio_pin *pin; + enum gpio_id id; + uint32_t en; + enum gpio_mode mode; + /* when GPIO comes from VBIOS, it has defined output state */ + enum gpio_pin_output_state output_state; +}; + +#if 0 +struct gpio_funcs { + + struct hw_gpio_pin *(*create_ddc_data)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_ddc_clock)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_generic)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_hpd)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_gpio_pad)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_sync)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + struct hw_gpio_pin *(*create_gsl)( + struct dc_context *ctx, + enum gpio_id id, + uint32_t en); + + /* HW translation */ + bool (*offset_to_id)( + uint32_t offset, + uint32_t mask, + enum gpio_id *id, + uint32_t *en); + bool (*id_to_offset)( + enum gpio_id id, + uint32_t en, + struct gpio_pin_info *info); +}; +#endif + +#endif /* __DAL_GPIO__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h new file mode 100644 index 000000000000..3b0e616f7066 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -0,0 +1,74 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_HW_SHARED_H__ +#define __DAL_HW_SHARED_H__ + +/****************************************************************************** + * Data types shared between different Virtual HW blocks + ******************************************************************************/ +struct gamma_curve { + uint32_t offset; + uint32_t segments_num; +}; + +struct curve_points { + struct fixed31_32 x; + struct fixed31_32 y; + struct fixed31_32 offset; + struct fixed31_32 slope; + + uint32_t custom_float_x; + uint32_t custom_float_y; + uint32_t custom_float_offset; + uint32_t custom_float_slope; +}; + +struct pwl_result_data { + struct fixed31_32 red; + struct fixed31_32 green; + struct fixed31_32 blue; + + struct fixed31_32 delta_red; + struct fixed31_32 delta_green; + struct fixed31_32 delta_blue; + + uint32_t red_reg; + uint32_t green_reg; + uint32_t blue_reg; + + uint32_t delta_red_reg; + uint32_t delta_green_reg; + uint32_t delta_blue_reg; +}; + +struct pwl_params { + uint32_t *data; + struct gamma_curve arr_curve_points[16]; + struct curve_points arr_points[3]; + struct pwl_result_data rgb_resulted[256 + 3]; + uint32_t hw_points_num; +}; +#endif /* __DAL_HW_SHARED_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h new file mode 100644 index 000000000000..7e5f3e02a719 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -0,0 +1,121 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_IPP_H__ +#define __DAL_IPP_H__ + +#include "hw_shared.h" + +#define MAXTRIX_COEFFICIENTS_NUMBER 12 +#define MAXTRIX_COEFFICIENTS_WRAP_NUMBER (MAXTRIX_COEFFICIENTS_NUMBER + 4) +#define MAX_OVL_MATRIX_COUNT 12 + +/* IPP RELATED */ +struct input_pixel_processor { + struct dc_context *ctx; + uint32_t inst; + const struct ipp_funcs *funcs; +}; + +enum ipp_prescale_mode { + IPP_PRESCALE_MODE_BYPASS, + IPP_PRESCALE_MODE_FIXED_SIGNED, + IPP_PRESCALE_MODE_FLOAT_SIGNED, + IPP_PRESCALE_MODE_FIXED_UNSIGNED, + IPP_PRESCALE_MODE_FLOAT_UNSIGNED +}; + +struct ipp_prescale_params { + enum ipp_prescale_mode mode; + uint16_t bias; + uint16_t scale; +}; + +enum ipp_degamma_mode { + IPP_DEGAMMA_MODE_BYPASS, + IPP_DEGAMMA_MODE_HW_sRGB, + IPP_DEGAMMA_MODE_HW_xvYCC, + IPP_DEGAMMA_MODE_USER_PWL +}; + +enum ovl_color_space { + OVL_COLOR_SPACE_UNKNOWN = 0, + OVL_COLOR_SPACE_RGB, + OVL_COLOR_SPACE_YUV601, + OVL_COLOR_SPACE_YUV709 +}; + +enum expansion_mode { + EXPANSION_MODE_DYNAMIC, + EXPANSION_MODE_ZERO +}; + +enum ipp_output_format { + IPP_OUTPUT_FORMAT_12_BIT_FIX, + IPP_OUTPUT_FORMAT_16_BIT_BYPASS, + IPP_OUTPUT_FORMAT_FLOAT +}; + +struct ipp_funcs { + + /*** cursor ***/ + void (*ipp_cursor_set_position)( + struct input_pixel_processor *ipp, + const struct dc_cursor_position *position); + + bool (*ipp_cursor_set_attributes)( + struct input_pixel_processor *ipp, + const struct dc_cursor_attributes *attributes); + + /*** setup input pixel processing ***/ + + /* put the entire pixel processor to bypass */ + void (*ipp_full_bypass)( + struct input_pixel_processor *ipp); + + /* setup ipp to expand/convert input to pixel processor internal format */ + void (*ipp_setup)( + struct input_pixel_processor *ipp, + enum surface_pixel_format input_format, + enum expansion_mode mode, + enum ipp_output_format output_format); + + /* DCE function to setup IPP. TODO: see if we can consolidate to setup */ + void (*ipp_program_prescale)( + struct input_pixel_processor *ipp, + struct ipp_prescale_params *params); + + /*** DEGAMMA RELATED ***/ + bool (*ipp_set_degamma)( + struct input_pixel_processor *ipp, + enum ipp_degamma_mode mode); + + bool (*ipp_program_degamma_pwl)( + struct input_pixel_processor *ipp, + const struct pwl_params *params); + +}; + +#endif /* __DAL_IPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h new file mode 100644 index 000000000000..77f8aa410898 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -0,0 +1,263 @@ +/* + * link_encoder.h + * + * Created on: Oct 6, 2015 + * Author: yonsun + */ + +#ifndef LINK_ENCODER_H_ +#define LINK_ENCODER_H_ + +#include "grph_object_defs.h" +#include "signal_types.h" +#include "dc_types.h" + +struct dc_context; +struct encoder_set_dp_phy_pattern_param; +struct link_mst_stream_allocation_table; +struct dc_link_settings; +struct link_training_settings; +struct core_stream; +struct pipe_ctx; + +struct encoder_init_data { + enum channel_id channel; + struct graphics_object_id connector; + enum hpd_source_id hpd_source; + /* TODO: in DAL2, here was pointer to EventManagerInterface */ + struct graphics_object_id encoder; + struct dc_context *ctx; + enum transmitter transmitter; +}; + +struct encoder_feature_support { + union { + struct { + /* 1 - external encoder; 0 - internal encoder */ + uint32_t EXTERNAL_ENCODER:1; + uint32_t ANALOG_ENCODER:1; + uint32_t STEREO_SYNC:1; + /* check the DDC data pin + * when performing DP Sink detection */ + uint32_t DP_SINK_DETECT_POLL_DATA_PIN:1; + /* CPLIB authentication + * for external DP chip supported */ + uint32_t CPLIB_DP_AUTHENTICATION:1; + uint32_t IS_HBR2_CAPABLE:1; + uint32_t IS_HBR3_CAPABLE:1; + uint32_t IS_HBR2_VALIDATED:1; + uint32_t IS_TPS3_CAPABLE:1; + uint32_t IS_TPS4_CAPABLE:1; + uint32_t IS_AUDIO_CAPABLE:1; + uint32_t IS_VCE_SUPPORTED:1; + uint32_t IS_CONVERTER:1; + uint32_t IS_Y_ONLY_CAPABLE:1; + uint32_t IS_YCBCR_CAPABLE:1; + } bits; + uint32_t raw; + } flags; + /* maximum supported deep color depth */ + enum dc_color_depth max_deep_color; + enum dc_color_depth max_hdmi_deep_color; + /* maximum supported clock */ + unsigned int max_pixel_clock; + unsigned int max_hdmi_pixel_clock; + bool ycbcr420_supported; +}; + +enum physical_phy_id { + PHYLD_0, + PHYLD_1, + PHYLD_2, + PHYLD_3, + PHYLD_4, + PHYLD_5, + PHYLD_6, + PHYLD_7, + PHYLD_8, + PHYLD_9, + PHYLD_COUNT, + PHYLD_UNKNOWN = (-1L) +}; + +enum phy_type { + PHY_TYPE_UNKNOWN = 1, + PHY_TYPE_PCIE_PHY = 2, + PHY_TYPE_UNIPHY = 3, +}; + +union dmcu_psr_level { + struct { + unsigned int SKIP_CRC:1; + unsigned int SKIP_DP_VID_STREAM_DISABLE:1; + unsigned int SKIP_PHY_POWER_DOWN:1; + unsigned int SKIP_AUX_ACK_CHECK:1; + unsigned int SKIP_CRTC_DISABLE:1; + unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; + unsigned int SKIP_SMU_NOTIFICATION:1; + unsigned int SKIP_AUTO_STATE_ADVANCE:1; + unsigned int DISABLE_PSR_ENTRY_ABORT:1; + unsigned int RESERVED:23; + } bits; + unsigned int u32all; +}; + +union dpcd_psr_configuration { + struct { + unsigned char ENABLE : 1; + unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1; + unsigned char CRC_VERIFICATION : 1; + unsigned char FRAME_CAPTURE_INDICATION : 1; + /* For eDP 1.4, PSR v2*/ + unsigned char LINE_CAPTURE_INDICATION : 1; + /* For eDP 1.4, PSR v2*/ + unsigned char IRQ_HPD_WITH_CRC_ERROR : 1; + unsigned char RESERVED : 2; + } bits; + unsigned char raw; +}; + +union psr_error_status { + struct { + unsigned char LINK_CRC_ERROR :1; + unsigned char RFB_STORAGE_ERROR :1; + unsigned char RESERVED :6; + } bits; + unsigned char raw; +}; + +union psr_sink_psr_status { + struct { + unsigned char SINK_SELF_REFRESH_STATUS :3; + unsigned char RESERVED :5; + } bits; + unsigned char raw; +}; + +struct psr_dmcu_context { + /* ddc line */ + enum channel_id channel; + /* Transmitter id */ + enum transmitter transmitterId; + /* Engine Id is used for Dig Be source select */ + enum engine_id engineId; + /* Controller Id used for Dig Fe source select */ + enum controller_id controllerId; + /* Pcie or Uniphy */ + enum phy_type phyType; + /* Physical PHY Id used by SMU interpretation */ + enum physical_phy_id smuPhyId; + /* Vertical total pixels from crtc timing. + * This is used for static screen detection. + * ie. If we want to detect half a frame, + * we use this to determine the hyst lines. + */ + unsigned int crtcTimingVerticalTotal; + /* PSR supported from panel capabilities and + * current display configuration + */ + bool psrSupportedDisplayConfig; + /* Whether fast link training is supported by the panel */ + bool psrExitLinkTrainingRequired; + /* If RFB setup time is greater than the total VBLANK time, + * it is not possible for the sink to capture the video frame + * in the same frame the SDP is sent. In this case, + * the frame capture indication bit should be set and an extra + * static frame should be transmitted to the sink. + */ + bool psrFrameCaptureIndicationReq; + /* Set the last possible line SDP may be transmitted without violating + * the RFB setup time or entering the active video frame. + */ + unsigned int sdpTransmitLineNumDeadline; + /* The VSync rate in Hz used to calculate the + * step size for smooth brightness feature + */ + unsigned int vsyncRateHz; + unsigned int skipPsrWaitForPllLock; + unsigned int numberOfControllers; + /* Unused, for future use. To indicate that first changed frame from + * state3 shouldn't result in psr_inactive, but rather to perform + * an automatic single frame rfb_update. + */ + bool rfb_update_auto_en; + /* Number of frame before entering static screen */ + unsigned int timehyst_frames; + /* Partial frames before entering static screen */ + unsigned int hyst_lines; + /* # of repeated AUX transaction attempts to make before + * indicating failure to the driver + */ + unsigned int aux_repeats; + /* Controls hw blocks to power down during PSR active state */ + union dmcu_psr_level psr_level; + /* Controls additional delay after remote frame capture before + * continuing powerd own + */ + unsigned int frame_delay; +}; + + +struct link_encoder { + const struct link_encoder_funcs *funcs; + int32_t aux_channel_offset; + struct dc_context *ctx; + struct graphics_object_id id; + struct graphics_object_id connector; + uint32_t input_signals; + uint32_t output_signals; + enum engine_id preferred_engine; + struct encoder_feature_support features; + enum transmitter transmitter; + enum hpd_source_id hpd_source; +}; + +struct link_encoder_funcs { + bool (*validate_output_with_stream)( + struct link_encoder *enc, struct pipe_ctx *pipe_ctx); + void (*hw_init)(struct link_encoder *enc); + void (*setup)(struct link_encoder *enc, + enum signal_type signal); + void (*enable_tmds_output)(struct link_encoder *enc, + enum clock_source_id clock_source, + enum dc_color_depth color_depth, + bool hdmi, + bool dual_link, + uint32_t pixel_clock); + void (*enable_dp_output)(struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + void (*enable_dp_mst_output)(struct link_encoder *enc, + const struct dc_link_settings *link_settings, + enum clock_source_id clock_source); + void (*disable_output)(struct link_encoder *link_enc, + enum signal_type signal); + void (*dp_set_lane_settings)(struct link_encoder *enc, + const struct link_training_settings *link_settings); + void (*dp_set_phy_pattern)(struct link_encoder *enc, + const struct encoder_set_dp_phy_pattern_param *para); + void (*update_mst_stream_allocation_table)( + struct link_encoder *enc, + const struct link_mst_stream_allocation_table *table); + void (*set_lcd_backlight_level) (struct link_encoder *enc, + uint32_t level); + void (*set_dmcu_backlight_level)(struct link_encoder *enc, + uint32_t level, uint32_t frame_ramp, uint32_t controller_id); + void (*init_dmcu_backlight_settings)(struct link_encoder *enc); + void (*set_dmcu_abm_level)(struct link_encoder *enc, uint32_t level); + void (*set_dmcu_psr_enable)(struct link_encoder *enc, bool enable); + void (*setup_dmcu_psr)(struct link_encoder *enc, + struct psr_dmcu_context *psr_context); + void (*backlight_control) (struct link_encoder *enc, + bool enable); + void (*power_control) (struct link_encoder *enc, + bool power_up); + void (*connect_dig_be_to_fe)(struct link_encoder *enc, + enum engine_id engine, + bool connect); + void (*enable_hpd)(struct link_encoder *enc); + void (*disable_hpd)(struct link_encoder *enc); + void (*destroy)(struct link_encoder **enc); +}; + +#endif /* LINK_ENCODER_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h new file mode 100644 index 000000000000..78dab74edc2d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -0,0 +1,106 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DAL_MEM_INPUT_H__ +#define __DAL_MEM_INPUT_H__ + +#include "dc.h" +#include "include/grph_object_id.h" +#include "inc/bandwidth_calcs.h" + +#include "dce/dce_mem_input.h" /* temporary */ + +struct stutter_modes { + bool enhanced; + bool quad_dmif_buffer; + bool watermark_nb_pstate; +}; + +struct mem_input { + struct mem_input_funcs *funcs; + struct dc_context *ctx; + struct dc_plane_address request_address; + struct dc_plane_address current_address; + uint32_t inst; + struct stutter_modes stutter_mode; + + const struct dce_mem_input_registers *regs; + const struct dce_mem_input_shift *shifts; + const struct dce_mem_input_mask *masks; + struct dce_mem_input_wa wa; +}; + +struct mem_input_funcs { + void (*mem_input_program_display_marks)( + struct mem_input *mem_input, + struct bw_watermarks nbp, + struct bw_watermarks stutter, + struct bw_watermarks urgent, + uint32_t total_dest_line_time_ns); + + void (*mem_input_program_chroma_display_marks)( + struct mem_input *mem_input, + struct bw_watermarks nbp, + struct bw_watermarks stutter, + struct bw_watermarks urgent, + uint32_t total_dest_line_time_ns); + + void (*allocate_mem_input)( + struct mem_input *mem_input, + uint32_t h_total,/* for current target */ + uint32_t v_total,/* for current target */ + uint32_t pix_clk_khz,/* for current target */ + uint32_t total_streams_num); + + void (*free_mem_input)( + struct mem_input *mem_input, + uint32_t paths_num); + + bool (*mem_input_program_surface_flip_and_addr)( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate); + + bool (*mem_input_program_pte_vm)( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + enum dc_rotation_angle rotation); + + bool (*mem_input_program_surface_config)( + struct mem_input *mem_input, + enum surface_pixel_format format, + union dc_tiling_info *tiling_info, + union plane_size *plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror); + + bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); + + void (*mem_input_update_dchub)(struct mem_input *mem_input, + struct dchub_init_data *dh_data); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h new file mode 100644 index 000000000000..e615997be20e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -0,0 +1,322 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_OPP_H__ +#define __DAL_OPP_H__ + +#include "hw_shared.h" +#include "transform.h" + +struct fixed31_32; +struct gamma_parameters; + +/* TODO: Need cleanup */ +enum clamping_range { + CLAMPING_FULL_RANGE = 0, /* No Clamping */ + CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */ + CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */ + CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */ + /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */ + CLAMPING_LIMITED_RANGE_PROGRAMMABLE +}; + +struct clamping_and_pixel_encoding_params { + enum dc_pixel_encoding pixel_encoding; /* Pixel Encoding */ + enum clamping_range clamping_level; /* Clamping identifier */ + enum dc_color_depth c_depth; /* Deep color use. */ +}; + +struct bit_depth_reduction_params { + struct { + /* truncate/round */ + /* trunc/round enabled*/ + uint32_t TRUNCATE_ENABLED:1; + /* 2 bits: 0=6 bpc, 1=8 bpc, 2 = 10bpc*/ + uint32_t TRUNCATE_DEPTH:2; + /* truncate or round*/ + uint32_t TRUNCATE_MODE:1; + + /* spatial dither */ + /* Spatial Bit Depth Reduction enabled*/ + uint32_t SPATIAL_DITHER_ENABLED:1; + /* 2 bits: 0=6 bpc, 1 = 8 bpc, 2 = 10bpc*/ + uint32_t SPATIAL_DITHER_DEPTH:2; + /* 0-3 to select patterns*/ + uint32_t SPATIAL_DITHER_MODE:2; + /* Enable RGB random dithering*/ + uint32_t RGB_RANDOM:1; + /* Enable Frame random dithering*/ + uint32_t FRAME_RANDOM:1; + /* Enable HighPass random dithering*/ + uint32_t HIGHPASS_RANDOM:1; + + /* temporal dither*/ + /* frame modulation enabled*/ + uint32_t FRAME_MODULATION_ENABLED:1; + /* same as for trunc/spatial*/ + uint32_t FRAME_MODULATION_DEPTH:2; + /* 2/4 gray levels*/ + uint32_t TEMPORAL_LEVEL:1; + uint32_t FRC25:2; + uint32_t FRC50:2; + uint32_t FRC75:2; + } flags; + + uint32_t r_seed_value; + uint32_t b_seed_value; + uint32_t g_seed_value; +}; + +enum wide_gamut_regamma_mode { + /* 0x0 - BITS2:0 Bypass */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_BYPASS, + /* 0x1 - Fixed curve sRGB 2.4 */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_SRGB24, + /* 0x2 - Fixed curve xvYCC 2.22 */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_XYYCC22, + /* 0x3 - Programmable control A */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_A, + /* 0x4 - Programmable control B */ + WIDE_GAMUT_REGAMMA_MODE_GRAPHICS_MATRIX_B, + /* 0x0 - BITS6:4 Bypass */ + WIDE_GAMUT_REGAMMA_MODE_OVL_BYPASS, + /* 0x1 - Fixed curve sRGB 2.4 */ + WIDE_GAMUT_REGAMMA_MODE_OVL_SRGB24, + /* 0x2 - Fixed curve xvYCC 2.22 */ + WIDE_GAMUT_REGAMMA_MODE_OVL_XYYCC22, + /* 0x3 - Programmable control A */ + WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_A, + /* 0x4 - Programmable control B */ + WIDE_GAMUT_REGAMMA_MODE_OVL_MATRIX_B +}; + +struct gamma_pixel { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; +}; + +enum channel_name { + CHANNEL_NAME_RED, + CHANNEL_NAME_GREEN, + CHANNEL_NAME_BLUE +}; + +struct custom_float_format { + uint32_t mantissa_bits; + uint32_t exponenta_bits; + bool sign; +}; + +struct custom_float_value { + uint32_t mantissa; + uint32_t exponenta; + uint32_t value; + bool negative; +}; + +struct hw_x_point { + uint32_t custom_float_x; + uint32_t custom_float_x_adjusted; + struct fixed31_32 x; + struct fixed31_32 adjusted_x; + struct fixed31_32 regamma_y_red; + struct fixed31_32 regamma_y_green; + struct fixed31_32 regamma_y_blue; + +}; + +struct pwl_float_data_ex { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; + struct fixed31_32 delta_r; + struct fixed31_32 delta_g; + struct fixed31_32 delta_b; +}; + +enum hw_point_position { + /* hw point sits between left and right sw points */ + HW_POINT_POSITION_MIDDLE, + /* hw point lays left from left (smaller) sw point */ + HW_POINT_POSITION_LEFT, + /* hw point lays stays from right (bigger) sw point */ + HW_POINT_POSITION_RIGHT +}; + +struct gamma_point { + int32_t left_index; + int32_t right_index; + enum hw_point_position pos; + struct fixed31_32 coeff; +}; + +struct pixel_gamma_point { + struct gamma_point r; + struct gamma_point g; + struct gamma_point b; +}; + +struct gamma_coefficients { + struct fixed31_32 a0[3]; + struct fixed31_32 a1[3]; + struct fixed31_32 a2[3]; + struct fixed31_32 a3[3]; + struct fixed31_32 user_gamma[3]; + struct fixed31_32 user_contrast; + struct fixed31_32 user_brightness; +}; + +struct pwl_float_data { + struct fixed31_32 r; + struct fixed31_32 g; + struct fixed31_32 b; +}; + +enum opp_regamma { + OPP_REGAMMA_BYPASS = 0, + OPP_REGAMMA_SRGB, + OPP_REGAMMA_3_6, + OPP_REGAMMA_USER, +}; + +struct output_pixel_processor { + struct dc_context *ctx; + uint32_t inst; + const struct opp_funcs *funcs; +}; + +enum fmt_stereo_action { + FMT_STEREO_ACTION_ENABLE = 0, + FMT_STEREO_ACTION_DISABLE, + FMT_STEREO_ACTION_UPDATE_POLARITY +}; + +enum graphics_csc_adjust_type { + GRAPHICS_CSC_ADJUST_TYPE_BYPASS = 0, + GRAPHICS_CSC_ADJUST_TYPE_HW, /* without adjustments */ + GRAPHICS_CSC_ADJUST_TYPE_SW /*use adjustments */ +}; + +struct default_adjustment { + enum lb_pixel_depth lb_color_depth; + enum dc_color_space out_color_space; + enum dc_color_space in_color_space; + enum dc_color_depth color_depth; + enum pixel_format surface_pixel_format; + enum graphics_csc_adjust_type csc_adjust_type; + bool force_hw_default; +}; + +enum grph_color_adjust_option { + GRPH_COLOR_MATRIX_HW_DEFAULT = 1, + GRPH_COLOR_MATRIX_SW +}; + +struct opp_grph_csc_adjustment { + enum grph_color_adjust_option color_adjust_option; + enum dc_color_space c_space; + enum dc_color_depth color_depth; /* clean up to uint32_t */ + enum graphics_csc_adjust_type csc_adjust_type; + int32_t adjust_divider; + int32_t grph_cont; + int32_t grph_sat; + int32_t grph_bright; + int32_t grph_hue; +}; + +struct out_csc_color_matrix { + enum dc_color_space color_space; + uint16_t regval[12]; +}; + +/* Underlay related types */ + +struct hw_adjustment_range { + int32_t hw_default; + int32_t min; + int32_t max; + int32_t step; + uint32_t divider; /* (actually HW range is min/divider; divider !=0) */ +}; + +enum ovl_csc_adjust_item { + OVERLAY_BRIGHTNESS = 0, + OVERLAY_GAMMA, + OVERLAY_CONTRAST, + OVERLAY_SATURATION, + OVERLAY_HUE, + OVERLAY_ALPHA, + OVERLAY_ALPHA_PER_PIX, + OVERLAY_COLOR_TEMPERATURE +}; + +struct opp_funcs { + void (*opp_power_on_regamma_lut)( + struct output_pixel_processor *opp, + bool power_on); + + bool (*opp_program_regamma_pwl)( + struct output_pixel_processor *opp, + const struct pwl_params *params); + + void (*opp_set_regamma_mode)(struct output_pixel_processor *opp, + enum opp_regamma mode); + + void (*opp_set_csc_adjustment)( + struct output_pixel_processor *opp, + const struct out_csc_color_matrix *tbl_entry); + + void (*opp_set_csc_default)( + struct output_pixel_processor *opp, + const struct default_adjustment *default_adjust); + + /* FORMATTER RELATED */ + + void (*opp_program_fmt)( + struct output_pixel_processor *opp, + struct bit_depth_reduction_params *fmt_bit_depth, + struct clamping_and_pixel_encoding_params *clamping); + + void (*opp_set_dyn_expansion)( + struct output_pixel_processor *opp, + enum dc_color_space color_sp, + enum dc_color_depth color_dpth, + enum signal_type signal); + + void (*opp_program_bit_depth_reduction)( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + + /* underlay related */ + void (*opp_get_underlay_adjustment_range)( + struct output_pixel_processor *opp, + enum ovl_csc_adjust_item overlay_adjust_item, + struct hw_adjustment_range *range); + + void (*opp_destroy)(struct output_pixel_processor **opp); +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h new file mode 100644 index 000000000000..9caf2b365420 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -0,0 +1,121 @@ +/* + * stream_encoder.h + * + */ + +#ifndef STREAM_ENCODER_H_ +#define STREAM_ENCODER_H_ + +#include "include/hw_sequencer_types.h" +#include "audio_types.h" + +struct dc_bios; +struct dc_context; +struct dc_crtc_timing; + +struct encoder_info_packet { + bool valid; + uint8_t hb0; + uint8_t hb1; + uint8_t hb2; + uint8_t hb3; + uint8_t sb[28]; +}; + +struct encoder_info_frame { + /* auxiliary video information */ + struct encoder_info_packet avi; + struct encoder_info_packet gamut; + struct encoder_info_packet vendor; + /* source product description */ + struct encoder_info_packet spd; + /* video stream configuration */ + struct encoder_info_packet vsc; +}; + +struct encoder_unblank_param { + struct hw_crtc_timing crtc_timing; + struct dc_link_settings link_settings; +}; + +struct encoder_set_dp_phy_pattern_param { + enum dp_test_pattern dp_phy_pattern; + const uint8_t *custom_pattern; + uint32_t custom_pattern_size; + enum dp_panel_mode dp_panel_mode; +}; + +struct stream_encoder { + const struct stream_encoder_funcs *funcs; + struct dc_context *ctx; + struct dc_bios *bp; + enum engine_id id; +}; + +struct stream_encoder_funcs { + void (*dp_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + enum dc_color_space output_color_space); + + void (*hdmi_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + int actual_pix_clk_khz, + bool enable_audio); + + void (*dvi_set_stream_attribute)( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + bool is_dual_link); + + void (*set_mst_bandwidth)( + struct stream_encoder *enc, + struct fixed31_32 avg_time_slots_per_mtp); + + void (*update_hdmi_info_packets)( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame); + + void (*stop_hdmi_info_packets)( + struct stream_encoder *enc); + + void (*update_dp_info_packets)( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame); + + void (*stop_dp_info_packets)( + struct stream_encoder *enc); + + void (*dp_blank)( + struct stream_encoder *enc); + + void (*dp_unblank)( + struct stream_encoder *enc, + const struct encoder_unblank_param *param); + + void (*audio_mute_control)( + struct stream_encoder *enc, bool mute); + + void (*dp_audio_setup)( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info); + + void (*dp_audio_enable) ( + struct stream_encoder *enc); + + void (*dp_audio_disable) ( + struct stream_encoder *enc); + + void (*hdmi_audio_setup)( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info, + struct audio_crtc_info *audio_crtc_info); + + void (*hdmi_audio_disable) ( + struct stream_encoder *enc); +}; + +#endif /* STREAM_ENCODER_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h new file mode 100644 index 000000000000..6ac609f6f89f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -0,0 +1,162 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_TIMING_GENERATOR_TYPES_H__ +#define __DAL_TIMING_GENERATOR_TYPES_H__ + +struct dc_bios; + +/** + * These parameters are required as input when doing blanking/Unblanking +*/ +#define MAX_TG_COLOR_VALUE 0x3FF + +struct tg_color { + /* Maximum 10 bits color value */ + uint16_t color_r_cr; + uint16_t color_g_y; + uint16_t color_b_cb; +}; + +/* Contains CRTC vertical/horizontal pixel counters */ +struct crtc_position { + uint32_t vertical_count; + uint32_t horizontal_count; + uint32_t nominal_vcount; +}; + +struct dcp_gsl_params { + int gsl_group; + int gsl_master; +}; + +#define LEFT_EYE_3D_PRIMARY_SURFACE 1 +#define RIGHT_EYE_3D_PRIMARY_SURFACE 0 + +enum test_pattern_dyn_range { + TEST_PATTERN_DYN_RANGE_VESA = 0, + TEST_PATTERN_DYN_RANGE_CEA +}; + +enum test_pattern_mode { + TEST_PATTERN_MODE_COLORSQUARES_RGB = 0, + TEST_PATTERN_MODE_COLORSQUARES_YCBCR601, + TEST_PATTERN_MODE_COLORSQUARES_YCBCR709, + TEST_PATTERN_MODE_VERTICALBARS, + TEST_PATTERN_MODE_HORIZONTALBARS, + TEST_PATTERN_MODE_SINGLERAMP_RGB, + TEST_PATTERN_MODE_DUALRAMP_RGB +}; + +enum test_pattern_color_format { + TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0, + TEST_PATTERN_COLOR_FORMAT_BPC_8, + TEST_PATTERN_COLOR_FORMAT_BPC_10, + TEST_PATTERN_COLOR_FORMAT_BPC_12 +}; + +enum controller_dp_test_pattern { + CONTROLLER_DP_TEST_PATTERN_D102 = 0, + CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR, + CONTROLLER_DP_TEST_PATTERN_PRBS7, + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES, + CONTROLLER_DP_TEST_PATTERN_VERTICALBARS, + CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS, + CONTROLLER_DP_TEST_PATTERN_COLORRAMP, + CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, + CONTROLLER_DP_TEST_PATTERN_RESERVED_8, + CONTROLLER_DP_TEST_PATTERN_RESERVED_9, + CONTROLLER_DP_TEST_PATTERN_RESERVED_A, + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA +}; + +enum crtc_state { + CRTC_STATE_VBLANK = 0, + CRTC_STATE_VACTIVE +}; + +struct timing_generator { + const struct timing_generator_funcs *funcs; + struct dc_bios *bp; + struct dc_context *ctx; + int inst; +}; + +struct dc_crtc_timing; + +struct drr_params; + +struct timing_generator_funcs { + bool (*validate_timing)(struct timing_generator *tg, + const struct dc_crtc_timing *timing); + void (*program_timing)(struct timing_generator *tg, + const struct dc_crtc_timing *timing, + bool use_vbios); + bool (*enable_crtc)(struct timing_generator *tg); + bool (*disable_crtc)(struct timing_generator *tg); + bool (*is_counter_moving)(struct timing_generator *tg); + void (*get_position)(struct timing_generator *tg, + int32_t *h_position, + int32_t *v_position); + uint32_t (*get_frame_count)(struct timing_generator *tg); + uint32_t (*get_scanoutpos)( + struct timing_generator *tg, + uint32_t *vbl, + uint32_t *position); + void (*set_early_control)(struct timing_generator *tg, + uint32_t early_cntl); + void (*wait_for_state)(struct timing_generator *tg, + enum crtc_state state); + bool (*set_blank)(struct timing_generator *tg, + bool enable_blanking); + bool (*is_blanked)(struct timing_generator *tg); + void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color); + void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color); + void (*set_colors)(struct timing_generator *tg, + const struct tg_color *blank_color, + const struct tg_color *overscan_color); + + void (*disable_vga)(struct timing_generator *tg); + bool (*did_triggered_reset_occur)(struct timing_generator *tg); + void (*setup_global_swap_lock)(struct timing_generator *tg, + const struct dcp_gsl_params *gsl_params); + void (*unlock)(struct timing_generator *tg); + void (*lock)(struct timing_generator *tg); + void (*enable_reset_trigger)(struct timing_generator *tg, int source_tg_inst); + void (*disable_reset_trigger)(struct timing_generator *tg); + void (*tear_down_global_swap_lock)(struct timing_generator *tg); + void (*enable_advanced_request)(struct timing_generator *tg, + bool enable, const struct dc_crtc_timing *timing); + void (*set_drr)(struct timing_generator *tg, const struct drr_params *params); + void (*set_static_screen_control)(struct timing_generator *tg, + uint32_t value); + void (*set_test_pattern)( + struct timing_generator *tg, + enum controller_dp_test_pattern test_pattern, + enum dc_color_depth color_depth); + +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h new file mode 100644 index 000000000000..ef743b70b3e9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -0,0 +1,179 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DAL_TRANSFORM_H__ +#define __DAL_TRANSFORM_H__ + +#include "dc_hw_types.h" +#include "fixed31_32.h" + +#define CSC_TEMPERATURE_MATRIX_SIZE 9 + +struct bit_depth_reduction_params; + +struct transform { + const struct transform_funcs *funcs; + struct dc_context *ctx; + int inst; +}; + +/* Colorimetry */ +enum colorimetry { + COLORIMETRY_NO_DATA = 0, + COLORIMETRY_ITU601 = 1, + COLORIMETRY_ITU709 = 2, + COLORIMETRY_EXTENDED = 3 +}; + +enum active_format_info { + ACTIVE_FORMAT_NO_DATA = 0, + ACTIVE_FORMAT_VALID = 1 +}; + +/* Active format aspect ratio */ +enum active_format_aspect_ratio { + ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE = 8, + ACTIVE_FORMAT_ASPECT_RATIO_4_3 = 9, + ACTIVE_FORMAT_ASPECT_RATIO_16_9 = 0XA, + ACTIVE_FORMAT_ASPECT_RATIO_14_9 = 0XB +}; + +enum bar_info { + BAR_INFO_NOT_VALID = 0, + BAR_INFO_VERTICAL_VALID = 1, + BAR_INFO_HORIZONTAL_VALID = 2, + BAR_INFO_BOTH_VALID = 3 +}; + +enum picture_scaling { + PICTURE_SCALING_UNIFORM = 0, + PICTURE_SCALING_HORIZONTAL = 1, + PICTURE_SCALING_VERTICAL = 2, + PICTURE_SCALING_BOTH = 3 +}; + +/* RGB quantization range */ +enum rgb_quantization_range { + RGB_QUANTIZATION_DEFAULT_RANGE = 0, + RGB_QUANTIZATION_LIMITED_RANGE = 1, + RGB_QUANTIZATION_FULL_RANGE = 2, + RGB_QUANTIZATION_RESERVED = 3 +}; + +/* YYC quantization range */ +enum yyc_quantization_range { + YYC_QUANTIZATION_LIMITED_RANGE = 0, + YYC_QUANTIZATION_FULL_RANGE = 1, + YYC_QUANTIZATION_RESERVED2 = 2, + YYC_QUANTIZATION_RESERVED3 = 3 +}; + +enum graphics_gamut_adjust_type { + GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS = 0, + GRAPHICS_GAMUT_ADJUST_TYPE_HW, /* without adjustments */ + GRAPHICS_GAMUT_ADJUST_TYPE_SW /* use adjustments */ +}; + +struct xfm_grph_csc_adjustment { + struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE]; + enum graphics_gamut_adjust_type gamut_adjust_type; +}; + +enum lb_pixel_depth { + /* do not change the values because it is used as bit vector */ + LB_PIXEL_DEPTH_18BPP = 1, + LB_PIXEL_DEPTH_24BPP = 2, + LB_PIXEL_DEPTH_30BPP = 4, + LB_PIXEL_DEPTH_36BPP = 8 +}; + +struct overscan_info { + int left; + int right; + int top; + int bottom; +}; + +struct scaling_ratios { + struct fixed31_32 horz; + struct fixed31_32 vert; + struct fixed31_32 horz_c; + struct fixed31_32 vert_c; +}; + +struct sharpness_adj { + int horz; + int vert; +}; + +struct line_buffer_params { + bool alpha_en; + bool pixel_expan_mode; + bool interleave_en; + int dynamic_pixel_depth; + enum lb_pixel_depth depth; +}; + +struct scaler_data { + int h_active; + int v_active; + struct scaling_taps taps; + struct rect viewport; + struct rect recout; + struct scaling_ratios ratios; + struct sharpness_adj sharpness; + enum pixel_format format; + struct line_buffer_params lb_params; +}; + +struct transform_funcs { + void (*transform_reset)(struct transform *xfm); + + void (*transform_set_scaler)(struct transform *xfm, + const struct scaler_data *scl_data); + + void (*transform_set_gamut_remap)( + struct transform *xfm, + const struct xfm_grph_csc_adjustment *adjust); + + void (*transform_set_pixel_storage_depth)( + struct transform *xfm, + enum lb_pixel_depth depth, + const struct bit_depth_reduction_params *bit_depth_params); + + bool (*transform_get_optimal_number_of_taps)( + struct transform *xfm, + struct scaler_data *scl_data, + const struct scaling_taps *in_taps); +}; + +extern const uint16_t filter_2tap_16p[18]; +extern const uint16_t filter_2tap_64p[66]; +const uint16_t *get_filter_3tap_16p(struct fixed31_32 ratio); +const uint16_t *get_filter_3tap_64p(struct fixed31_32 ratio); +const uint16_t *get_filter_4tap_16p(struct fixed31_32 ratio); +const uint16_t *get_filter_4tap_64p(struct fixed31_32 ratio); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h new file mode 100644 index 000000000000..35a556dd9054 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -0,0 +1,156 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HW_SEQUENCER_H__ +#define __DC_HW_SEQUENCER_H__ +#include "core_types.h" +#include "timing_generator.h" + +struct gamma_parameters; + +enum pipe_gating_control { + PIPE_GATING_CONTROL_DISABLE = 0, + PIPE_GATING_CONTROL_ENABLE, + PIPE_GATING_CONTROL_INIT +}; + +enum pipe_lock_control { + PIPE_LOCK_CONTROL_GRAPHICS = 1 << 0, + PIPE_LOCK_CONTROL_BLENDER = 1 << 1, + PIPE_LOCK_CONTROL_SCL = 1 << 2, + PIPE_LOCK_CONTROL_SURFACE = 1 << 3, + PIPE_LOCK_CONTROL_MODE = 1 << 4 +}; + +struct dce_hwseq; + +struct hw_sequencer_funcs { + + void (*init_hw)(struct core_dc *dc); + + enum dc_status (*apply_ctx_to_hw)( + struct core_dc *dc, struct validate_context *context); + + void (*reset_hw_ctx_wrap)( + struct core_dc *dc, struct validate_context *context); + + void (*prepare_pipe_for_context)( + struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct validate_context *context); + + void (*apply_ctx_for_surface)( + struct core_dc *dc, + struct core_surface *surface, + struct validate_context *context); + + void (*set_plane_config)( + const struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct resource_context *res_ctx); + + void (*update_plane_addr)( + const struct core_dc *dc, + struct pipe_ctx *pipe_ctx); + + void (*update_pending_status)( + struct pipe_ctx *pipe_ctx); + + bool (*set_gamma_correction)( + struct input_pixel_processor *ipp, + struct output_pixel_processor *opp, + const struct core_gamma *ramp, + const struct core_surface *surface); + + void (*power_down)(struct core_dc *dc); + + void (*enable_accelerated_mode)(struct core_dc *dc); + + void (*enable_timing_synchronization)( + struct core_dc *dc, + int group_index, + int group_size, + struct pipe_ctx *grouped_pipes[]); + + /* backlight control */ + void (*encoder_set_lcd_backlight_level)( + struct link_encoder *enc, uint32_t level); + + void (*enable_display_pipe_clock_gating)( + struct dc_context *ctx, + bool clock_gating); + + bool (*enable_display_power_gating)( + struct core_dc *dc, + uint8_t controller_id, + struct dc_bios *dcb, + enum pipe_gating_control power_gating); + + void (*power_down_front_end)(struct core_dc *dc, struct pipe_ctx *pipe); + void (*update_info_frame)(struct pipe_ctx *pipe_ctx); + + void (*enable_stream)(struct pipe_ctx *pipe_ctx); + + void (*disable_stream)(struct pipe_ctx *pipe_ctx); + + void (*unblank_stream)(struct pipe_ctx *pipe_ctx, + struct dc_link_settings *link_settings); + + void (*pipe_control_lock)( + struct dce_hwseq *hwseq, + unsigned int blnd_inst, + enum pipe_lock_control control_mask, + bool lock); + + void (*set_displaymarks)( + const struct core_dc *dc, + struct validate_context *context); + + void (*increase_watermarks_for_pipe)(struct core_dc *dc, + struct pipe_ctx *pipe_ctx, + struct validate_context *context); + + void (*set_display_clock)(struct validate_context *context); + + void (*set_bandwidth)(struct core_dc *dc); + + void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, + int vmin, int vmax); + + void (*set_static_screen_control)(struct pipe_ctx **pipe_ctx, + int num_pipes, int value); + + enum dc_status (*prog_pixclk_crtc_otg)( + struct pipe_ctx *pipe_ctx, + struct validate_context *context, + struct core_dc *dc); +}; + +void color_space_to_black_color( + const struct core_dc *dc, + enum dc_color_space colorspace, + struct tg_color *black_color); + +#endif /* __DC_HW_SEQUENCER_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h new file mode 100644 index 000000000000..662fa30d45f7 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h @@ -0,0 +1,73 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_LINK_HWSS_H__ +#define __DC_LINK_HWSS_H__ + +#include "inc/core_status.h" + +enum dc_status core_link_read_dpcd( + struct core_link* link, + uint32_t address, + uint8_t *data, + uint32_t size); + +enum dc_status core_link_write_dpcd( + struct core_link* link, + uint32_t address, + const uint8_t *data, + uint32_t size); + +void dp_enable_link_phy( + struct core_link *link, + enum signal_type signal, + enum clock_source_id clock_source, + const struct dc_link_settings *link_settings); + +void dp_receiver_power_ctrl(struct core_link *link, bool on); + +void dp_disable_link_phy(struct core_link *link, enum signal_type signal); + +void dp_disable_link_phy_mst(struct core_link *link, enum signal_type signal); + +bool dp_set_hw_training_pattern( + struct core_link *link, + enum hw_dp_training_pattern pattern); + +void dp_set_hw_lane_settings( + struct core_link *link, + const struct link_training_settings *link_settings); + +void dp_set_hw_test_pattern( + struct core_link *link, + enum dp_test_pattern test_pattern, + uint8_t *custom_pattern, + uint32_t custom_pattern_size); + +enum dp_panel_mode dp_get_panel_mode(struct core_link *link); + +void dp_retrain_link(struct core_link *link); + +#endif /* __DC_LINK_HWSS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h new file mode 100644 index 000000000000..159b2c519f2b --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h @@ -0,0 +1,290 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ +#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ + +#include "dm_services.h" + +/* macro for register read/write + * user of macro need to define + * + * CTX ==> macro to ptr to dc_context + * eg. aud110->base.ctx + * + * REG ==> macro to location of register offset + * eg. aud110->regs->reg + */ +#define REG_READ(reg_name) \ + dm_read_reg(CTX, REG(reg_name)) + +#define REG_WRITE(reg_name, value) \ + dm_write_reg(CTX, REG(reg_name), value) + +#ifdef REG_SET +#undef REG_SET +#endif + +#ifdef REG_GET +#undef REG_GET +#endif + +/* macro to set register fields. */ +#define REG_SET_N(reg_name, n, initial_val, ...) \ + generic_reg_update_ex(CTX, \ + REG(reg_name), \ + initial_val, \ + n, __VA_ARGS__) + +#define FN(reg_name, field) \ + FD(reg_name##__##field) + +#define REG_SET(reg_name, initial_val, field, val) \ + REG_SET_N(reg_name, 1, initial_val, \ + FN(reg_name, field), val) + +#define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ + REG_SET_N(reg, 2, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2) + +#define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ + REG_SET_N(reg, 3, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2,\ + FN(reg, f3), v3) + +#define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ + REG_SET_N(reg, 4, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2,\ + FN(reg, f3), v3,\ + FN(reg, f4), v4) + +#define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ + f5, v5) \ + REG_SET_N(reg, 6, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2,\ + FN(reg, f3), v3,\ + FN(reg, f4), v4,\ + FN(reg, f5), v5) + +#define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ + f5, v5, f6, v6) \ + REG_SET_N(reg, 6, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2,\ + FN(reg, f3), v3,\ + FN(reg, f4), v4,\ + FN(reg, f5), v5,\ + FN(reg, f6), v6) + +#define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ + f5, v5, f6, v6, f7, v7) \ + REG_SET_N(reg, 7, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2,\ + FN(reg, f3), v3,\ + FN(reg, f4), v4,\ + FN(reg, f5), v5,\ + FN(reg, f6), v6,\ + FN(reg, f7), v7) + +#define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \ + v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ + REG_SET_N(reg, 10, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3, \ + FN(reg, f4), v4, \ + FN(reg, f5), v5, \ + FN(reg, f6), v6, \ + FN(reg, f7), v7, \ + FN(reg, f8), v8, \ + FN(reg, f9), v9, \ + FN(reg, f10), v10) + +/* macro to get register fields + * read given register and fill in field value in output parameter */ +#define REG_GET(reg_name, field, val) \ + generic_reg_get(CTX, REG(reg_name), \ + FN(reg_name, field), val) + +#define REG_GET_2(reg_name, f1, v1, f2, v2) \ + generic_reg_get2(CTX, REG(reg_name), \ + FN(reg_name, f1), v1, \ + FN(reg_name, f2), v2) + +#define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3) \ + generic_reg_get3(CTX, REG(reg_name), \ + FN(reg_name, f1), v1, \ + FN(reg_name, f2), v2, \ + FN(reg_name, f3), v3) + +#define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + generic_reg_get5(CTX, REG(reg_name), \ + FN(reg_name, f1), v1, \ + FN(reg_name, f2), v2, \ + FN(reg_name, f3), v3, \ + FN(reg_name, f4), v4, \ + FN(reg_name, f5), v5) + +/* macro to poll and wait for a register field to read back given value */ + +#define REG_WAIT(reg_name, field, val, delay, max_try) \ + generic_reg_wait(CTX, \ + REG(reg_name), FN(reg_name, field), val,\ + delay, max_try, __func__) + +/* macro to update (read, modify, write) register fields + */ +#define REG_UPDATE_N(reg_name, n, ...) \ + generic_reg_update_ex(CTX, \ + REG(reg_name), \ + REG_READ(reg_name), \ + n, __VA_ARGS__) + +#define REG_UPDATE(reg_name, field, val) \ + REG_UPDATE_N(reg_name, 1, \ + FN(reg_name, field), val) + +#define REG_UPDATE_2(reg, f1, v1, f2, v2) \ + REG_UPDATE_N(reg, 2,\ + FN(reg, f1), v1,\ + FN(reg, f2), v2) + +#define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ + REG_UPDATE_N(reg, 3, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3) + +#define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ + REG_UPDATE_N(reg, 4, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3, \ + FN(reg, f4), v4) + +#define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ + REG_UPDATE_N(reg, 5, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3, \ + FN(reg, f4), v4, \ + FN(reg, f5), v5) + +#define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ + REG_UPDATE_N(reg, 6, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3, \ + FN(reg, f4), v4, \ + FN(reg, f5), v5, \ + FN(reg, f6), v6) + +#define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ + REG_UPDATE_N(reg, 7, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3, \ + FN(reg, f4), v4, \ + FN(reg, f5), v5, \ + FN(reg, f6), v6, \ + FN(reg, f7), v7) + +#define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ + REG_UPDATE_N(reg, 8, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3, \ + FN(reg, f4), v4, \ + FN(reg, f5), v5, \ + FN(reg, f6), v6, \ + FN(reg, f7), v7, \ + FN(reg, f8), v8) + +#define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9) \ + REG_UPDATE_N(reg, 9, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3, \ + FN(reg, f4), v4, \ + FN(reg, f5), v5, \ + FN(reg, f6), v6, \ + FN(reg, f7), v7, \ + FN(reg, f8), v8, \ + FN(reg, f9), v9) + +#define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10) \ + REG_UPDATE_N(reg, 10, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2, \ + FN(reg, f3), v3, \ + FN(reg, f4), v4, \ + FN(reg, f5), v5, \ + FN(reg, f6), v6, \ + FN(reg, f7), v7, \ + FN(reg, f8), v8, \ + FN(reg, f9), v9, \ + FN(reg, f10), v10) + +/* macro to update a register field to specified values in given sequences. + * useful when toggling bits + */ +#define REG_UPDATE_SEQ(reg, field, value1, value2) \ +{ uint32_t val = REG_UPDATE(reg, field, value1); \ + REG_SET(reg, val, field, value2); } + +/* macro to update fields in register 1 field at a time in given order */ +#define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \ +{ uint32_t val = REG_UPDATE(reg, f1, v1); \ + REG_SET(reg, val, f2, v2); } + +#define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \ +{ uint32_t val = REG_UPDATE(reg, f1, v1); \ + val = REG_SET(reg, val, f2, v2); \ + REG_SET(reg, val, f3, v3); } + +uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr, + uint8_t shift, uint32_t mask, uint32_t *field_value); + +uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2); + +uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2, + uint8_t shift3, uint32_t mask3, uint32_t *field_value3); + +uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr, + uint8_t shift1, uint32_t mask1, uint32_t *field_value1, + uint8_t shift2, uint32_t mask2, uint32_t *field_value2, + uint8_t shift3, uint32_t mask3, uint32_t *field_value3, + uint8_t shift4, uint32_t mask4, uint32_t *field_value4, + uint8_t shift5, uint32_t mask5, uint32_t *field_value5); + +#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h new file mode 100644 index 000000000000..8dd676de6b07 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -0,0 +1,164 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + */ + +#ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ +#define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ + +#include "core_types.h" +#include "core_status.h" +#include "core_dc.h" +#include "dal_asic_id.h" + +/* TODO unhardcode, 4 for CZ*/ +#define MEMORY_TYPE_MULTIPLIER 4 + +enum dce_version resource_parse_asic_id( + struct hw_asic_id asic_id); + +struct resource_caps { + int num_timing_generator; + int num_video_plane; + int num_audio; + int num_stream_encoder; + int num_pll; +}; + +struct resource_straps { + uint32_t hdmi_disable; + uint32_t dc_pinstraps_audio; + uint32_t audio_stream_number; +}; + +struct resource_create_funcs { + void (*read_dce_straps)( + struct dc_context *ctx, struct resource_straps *straps); + + struct audio *(*create_audio)( + struct dc_context *ctx, unsigned int inst); + + struct stream_encoder *(*create_stream_encoder)( + enum engine_id eng_id, struct dc_context *ctx); + + struct dce_hwseq *(*create_hwseq)( + struct dc_context *ctx); +}; + +bool resource_construct( + unsigned int num_virtual_links, + struct core_dc *dc, + struct resource_pool *pool, + const struct resource_create_funcs *create_funcs); + +struct resource_pool *dc_create_resource_pool( + struct core_dc *dc, + int num_virtual_links, + enum dce_version dc_version, + struct hw_asic_id asic_id); + +void dc_destroy_resource_pool(struct core_dc *dc); + +enum dc_status resource_map_pool_resources( + const struct core_dc *dc, + struct validate_context *context); + +bool resource_build_scaling_params( + const struct dc_surface *surface, + struct pipe_ctx *pipe_ctx); + +enum dc_status resource_build_scaling_params_for_context( + const struct core_dc *dc, + struct validate_context *context); + +void resource_build_info_frame(struct pipe_ctx *pipe_ctx); + +void resource_unreference_clock_source( + struct resource_context *res_ctx, + struct clock_source *clock_source); + +void resource_reference_clock_source( + struct resource_context *res_ctx, + struct clock_source *clock_source); + +bool resource_are_streams_timing_synchronizable( + const struct core_stream *stream1, + const struct core_stream *stream2); + +struct clock_source *resource_find_used_clk_src_for_sharing( + struct resource_context *res_ctx, + struct pipe_ctx *pipe_ctx); + +struct clock_source *dc_resource_find_first_free_pll( + struct resource_context *res_ctx); + +struct pipe_ctx *resource_get_head_pipe_for_stream( + struct resource_context *res_ctx, + const struct core_stream *stream); + +bool resource_attach_surfaces_to_context( + const struct dc_surface *const *surfaces, + int surface_count, + const struct dc_target *dc_target, + struct validate_context *context); + +struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx); + +bool resource_is_stream_unchanged( + const struct validate_context *old_context, struct core_stream *stream); + +bool is_target_unchanged( + const struct core_target *old_target, const struct core_target *target); +bool resource_validate_attach_surfaces( + const struct dc_validation_set set[], + int set_count, + const struct validate_context *old_context, + struct validate_context *context); + +void validate_guaranteed_copy_target( + struct validate_context *context, + int max_targets); + +void resource_validate_ctx_update_pointer_after_copy( + const struct validate_context *src_ctx, + struct validate_context *dst_ctx); + +void resource_validate_ctx_copy_construct( + const struct validate_context *src_ctx, + struct validate_context *dst_ctx); + +void resource_validate_ctx_destruct(struct validate_context *context); + +enum dc_status resource_map_clock_resources( + const struct core_dc *dc, + struct validate_context *context); + +enum dc_status resource_map_phy_clock_resources( + const struct core_dc *dc, + struct validate_context *context); + +bool pipe_need_reprogram( + struct pipe_ctx *pipe_ctx_old, + struct pipe_ctx *pipe_ctx); + + +#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ |