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path: root/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 4302f9be1a7d..901e3b531a12 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1173,24 +1173,6 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign
return odm_combine_factor;
}
-void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
-{
- uint32_t pix_per_cycle = 1;
- uint32_t odm_combine_factor = 1;
-
- if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc)
- return;
-
- odm_combine_factor = get_odm_config(pipe_ctx, NULL);
- if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing) || odm_combine_factor > 1
- || dcn32_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
- pix_per_cycle = 2;
-
- if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
- pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
- pix_per_cycle);
-}
-
void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context)
{
unsigned int i;