diff options
Diffstat (limited to 'Documentation/devicetree')
6 files changed, 202 insertions, 125 deletions
diff --git a/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml new file mode 100644 index 000000000000..de9a465096db --- /dev/null +++ b/Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/arm,syscon-icst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM System Controller ICST Clocks + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: | + The ICS525 and ICS307 oscillators are produced by Integrated + Devices Technology (IDT). ARM integrated these oscillators deeply into their + reference designs by adding special control registers that manage such + oscillators to their system controllers. + + The various ARM system controllers contain logic to serialize and initialize + an ICST clock request after a write to the 32 bit register at an offset + into the system controller. Furthermore, to even be able to alter one of + these frequencies, the system controller must first be unlocked by + writing a special token to another offset in the system controller. + + Some ARM hardware contain special versions of the serial interface that only + connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to + different values and sometimes also hard-wires the output divider. They + therefore have special compatible strings as per this table (the OD value is + the value on the pins, not the resulting output divider). + + In the core modules and logic tiles, the ICST is a configurable clock fed + from a 24 MHz clock on the motherboard (usually the main crystal) used for + generating e.g. video clocks. It is located on the core module and there is + only one of these. This clock node must be a subnode of the core module. + + Hardware variant RDW OD VDW + + Integrator/AP 22 1 Bit 8 0, rest variable + integratorap-cm + + Integrator/AP 46 3 Bit 8 0, rest variable + integratorap-sys + + Integrator/AP 22 or 1 17 or (33 or 25 MHz) + integratorap-pci 14 1 14 + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-core + + Integrator/CP 22 variable Bit 8 0, rest variable + integratorcp-cm-mem + + The ICST oscillator must be provided inside a system controller node. + +properties: + "#clock-cells": + const: 0 + + compatible: + enum: + - arm,syscon-icst525 + - arm,syscon-icst307 + - arm,syscon-icst525-integratorap-cm + - arm,syscon-icst525-integratorap-sys + - arm,syscon-icst525-integratorap-pci + - arm,syscon-icst525-integratorcp-cm-core + - arm,syscon-icst525-integratorcp-cm-mem + - arm,integrator-cm-auxosc + - arm,versatile-cm-auxosc + - arm,impd-vco1 + - arm,impd-vco2 + + clocks: + description: Parent clock for the ICST VCO + maxItems: 1 + + clock-output-names: + maxItems: 1 + + lock-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Offset to the unlocking register for the oscillator + + vco-offset: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Offset to the VCO register for the oscillator + +required: + - "#clock-cells" + - compatible + - clocks + +examples: + - | + vco1: clock@00 { + compatible = "arm,impd1-vco1"; + #clock-cells = <0>; + lock-offset = <0x08>; + vco-offset = <0x00>; + clocks = <&sysclk>; + clock-output-names = "IM-PD1-VCO1"; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt deleted file mode 100644 index 11f5f95f571b..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-integrator.txt +++ /dev/null @@ -1,34 +0,0 @@ -Clock bindings for ARM Integrator and Versatile Core Module clocks - -Auxiliary Oscillator Clock - -This is a configurable clock fed from a 24 MHz chrystal, -used for generating e.g. video clocks. It is located on the -core module and there is only one of these. - -This clock node *must* be a subnode of the core module, since -it obtains the base address for it's address range from its -parent node. - - -Required properties: -- compatible: must be "arm,integrator-cm-auxosc" or "arm,versatile-cm-auxosc" -- #clock-cells: must be <0> - -Optional properties: -- clocks: parent clock(s) - -Example: - -core-module@10000000 { - xtal24mhz: xtal24mhz@24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - auxosc: cm_aux_osc@25M { - #clock-cells = <0>; - compatible = "arm,integrator-cm-auxosc"; - clocks = <&xtal24mhz>; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt b/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt deleted file mode 100644 index 4cd81742038f..000000000000 --- a/Documentation/devicetree/bindings/clock/arm-syscon-icst.txt +++ /dev/null @@ -1,70 +0,0 @@ -ARM System Controller ICST clocks - -The ICS525 and ICS307 oscillators are produced by Integrated Devices -Technology (IDT). ARM integrated these oscillators deeply into their -reference designs by adding special control registers that manage such -oscillators to their system controllers. - -The various ARM system controllers contain logic to serialize and initialize -an ICST clock request after a write to the 32 bit register at an offset -into the system controller. Furthermore, to even be able to alter one of -these frequencies, the system controller must first be unlocked by -writing a special token to another offset in the system controller. - -Some ARM hardware contain special versions of the serial interface that only -connects the low 8 bits of the VDW (missing one bit), hardwires RDW to -different values and sometimes also hardwire the output divider. They -therefore have special compatible strings as per this table (the OD value is -the value on the pins, not the resulting output divider): - -Hardware variant: RDW OD VDW - -Integrator/AP 22 1 Bit 8 0, rest variable -integratorap-cm - -Integrator/AP 46 3 Bit 8 0, rest variable -integratorap-sys - -Integrator/AP 22 or 1 17 or (33 or 25 MHz) -integratorap-pci 14 1 14 - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-core - -Integrator/CP 22 variable Bit 8 0, rest variable -integratorcp-cm-mem - -The ICST oscillator must be provided inside a system controller node. - -Required properties: -- compatible: must be one of - "arm,syscon-icst525" - "arm,syscon-icst307" - "arm,syscon-icst525-integratorap-cm" - "arm,syscon-icst525-integratorap-sys" - "arm,syscon-icst525-integratorap-pci" - "arm,syscon-icst525-integratorcp-cm-core" - "arm,syscon-icst525-integratorcp-cm-mem" -- lock-offset: the offset address into the system controller where the - unlocking register is located -- vco-offset: the offset address into the system controller where the - ICST control register is located (even 32 bit address) -- #clock-cells: must be <0> -- clocks: parent clock, since the ICST needs a parent clock to derive its - frequency from, this attribute is compulsory. - -Example: - -syscon: syscon@10000000 { - compatible = "syscon"; - reg = <0x10000000 0x1000>; - - oscclk0: osc0@c { - compatible = "arm,syscon-icst307"; - #clock-cells = <0>; - lock-offset = <0x20>; - vco-offset = <0x0c>; - clocks = <&xtal24mhz>; - }; - (...) -}; diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml new file mode 100644 index 000000000000..e2b6ac96bbcb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,mmp2-clock.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/marvell,mmp2-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell MMP2 and MMP3 Clock Controller + +maintainers: + - Lubomir Rintel <lkundrak@v3.sk> + +description: | + The clock subsystem on MMP2 or MMP3 generates and supplies clock to various + controllers within the SoC. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. + +properties: + compatible: + enum: + - marvell,mmp2-clock # controller compatible with MMP2 SoC + - marvell,mmp3-clock # controller compatible with MMP3 SoC + + reg: + items: + - description: MPMU register region + - description: APMU register region + - description: APBC register region + + reg-names: + items: + - const: mpmu + - const: apmu + - const: apbc + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@d4050000 { + compatible = "marvell,mmp2-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt deleted file mode 100644 index 23b52dc02266..000000000000 --- a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Marvell MMP2 Clock Controller - -The MMP2 clock subsystem generates and supplies clock to various -controllers within the MMP2 SoC. - -Required Properties: - -- compatible: should be one of the following. - - "marvell,mmp2-clock" - controller compatible with MMP2 SoC. - -- reg: physical base address of the clock subsystem and length of memory mapped - region. There are 3 places in SOC has clock control logic: - "mpmu", "apmu", "apbc". So three reg spaces need to be defined. - -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Each clock is assigned an identifier and client nodes use this identifier -to specify the clock which they consume. - -All these identifiers could be found in <dt-bindings/clock/marvell,mmp2.h>. diff --git a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file mode 100644 index 000000000000..869b18ac88d7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI EHRPWM Time Base Clock + +maintainers: + - Vignesh Raghavendra <vigneshr@ti.com> + +properties: + compatible: + items: + - const: ti,am654-ehrpwm-tbclk + - const: syscon + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +examples: + - | + ehrpwm_tbclk: syscon@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; |