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| author | YR Yang <yr.yang@mediatek.com> | 2024-08-01 16:43:26 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2024-08-14 21:56:34 +0100 |
| commit | ff9f065318e17a1a97981d9e535fcfc6ce5d5614 (patch) | |
| tree | 03c50c5a1d40085fb607aff4482f157bc95f10c2 /sound/soc/ux500 | |
| parent | 2251db28edcc70b7ee8a8c6bcbaecf752b3ea5ec (diff) | |
| download | linux-ff9f065318e17a1a97981d9e535fcfc6ce5d5614.tar.gz linux-ff9f065318e17a1a97981d9e535fcfc6ce5d5614.tar.bz2 linux-ff9f065318e17a1a97981d9e535fcfc6ce5d5614.zip | |
ASoC: mediatek: mt8188: Mark AFE_DAC_CON0 register as volatile
Add AFE Control Register 0 to the volatile_register.
AFE_DAC_CON0 can be modified by both the SOF and ALSA drivers.
If this register is read and written in cache mode, the cached value
might not reflect the actual value when the register is modified by
another driver. It can cause playback or capture failures. Therefore,
it is necessary to add AFE_DAC_CON0 to the list of volatile registers.
Signed-off-by: YR Yang <yr.yang@mediatek.com>
Reviewed-by: Fei Shao <fshao@chromium.org>
Reviewed-by: Trevor Wu <trevor.wu@mediatek.com>
Link: https://patch.msgid.link/20240801084326.1472-1-yr.yang@mediatek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/ux500')
0 files changed, 0 insertions, 0 deletions