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| author | Mike Travis <mike.travis@hpe.com> | 2022-04-06 14:51:48 -0500 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-04-07 17:24:39 +0200 |
| commit | bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec (patch) | |
| tree | 3534ad1cb685b43d75f0afdb4b9e0bbdcec6f596 /mm/mincore.c | |
| parent | d812f7c475c6a4dcfff02a85fbfd7a9c87e6a094 (diff) | |
| download | linux-bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec.tar.gz linux-bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec.tar.bz2 linux-bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec.zip | |
x86/platform/uv: Update TSC sync state for UV5
The UV5 platform synchronizes the TSCs among all chassis, and will not
proceed to OS boot without achieving synchronization. Previous UV
platforms provided a register indicating successful synchronization.
This is no longer available on UV5. On this platform TSC_ADJUST
should not be reset by the kernel.
Signed-off-by: Mike Travis <mike.travis@hpe.com>
Signed-off-by: Steve Wahl <steve.wahl@hpe.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Dimitri Sivanich <dimitri.sivanich@hpe.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20220406195149.228164-3-steve.wahl@hpe.com
Diffstat (limited to 'mm/mincore.c')
0 files changed, 0 insertions, 0 deletions