Merge tag 'i3c/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux

Pull i3c updates from Alexandre Belloni:
 "Core:
   - avoid possible deadlock on probe
   - ensured preferred address is used on hot-join

  Drivers:
   - dw: add AMD I3C controller support
   - mipi-i3c-hci: fix SETDASA, DMA interrupts fixes
   - svc: many fixes for IBI and hotjoin"

* tag 'i3c/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux:
  i3c: Use i3cdev->desc->info instead of calling i3c_device_get_info() to avoid deadlock
  i3c: mipi-i3c-hci: Support SETDASA CCC
  i3c: dw: Add quirk to address OD/PP timing issue on AMD platform
  i3c: dw: Add support for AMDI0015 ACPI ID
  i3c: master: svc: Modify enabled_events bit 7:0 to act as IBI enable counter
  i3c: Document I3C_ADDR_SLOT_EXT_STATUS_MASK
  i3c: master: svc: Fix pm_runtime_set_suspended() with runtime pm enabled
  i3c: mipi-i3c-hci: Handle interrupts according to current specifications
  i3c: mipi-i3c-hci: Mask ring interrupts before ring stop request
  i3c: master: Fix miss free init_dyn_addr at i3c_master_put_i3c_addrs()
  i3c: master: Remove i3c_dev_disable_ibi_locked(olddev) on device hotjoin
  i3c: master: svc: fix possible assignment of the same address to two devices
  i3c: master: svc: wait for Manual ACK/NACK Done before next step
  i3c: master: svc: use spin_lock_irqsave at svc_i3c_master_ibi_work()
  i3c: master: svc: need check IBIWON for dynamic address assignment
  i3c: master: svc: manually emit NACK/ACK for hotjoin
  i3c: master: svc: use repeat start when IBI WIN happens
  i3c: master: Fix dynamic address leak when 'assigned-address' is present
  i3c: master: Extend address status bit to 4 and add I3C_ADDR_SLOT_EXT_DESIRED
  i3c: master: Replace hard code 2 with macro I3C_ADDR_SLOT_STATUS_BITS

1 files changed, 8 insertions, 2 deletions

diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
index 2a1ed05d5782..12d532b012c5 100644
--- a/include/linux/i3c/master.h
+++ b/include/linux/i3c/master.h
@@ -298,7 +298,9 @@ enum i3c_open_drain_speed {
  * @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device
  * @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device
  * @I3C_ADDR_SLOT_STATUS_MASK: address slot mask
- *
+ * @I3C_ADDR_SLOT_EXT_STATUS_MASK: address slot mask with extended information
+ * @I3C_ADDR_SLOT_EXT_DESIRED: the bitmask represents addresses that are preferred by some devices,
+ *			       such as the "assigned-address" property in a device tree source.
  * On an I3C bus, addresses are assigned dynamically, and we need to know which
  * addresses are free to use and which ones are already assigned.
  *
@@ -311,8 +313,12 @@ enum i3c_addr_slot_status {
 	I3C_ADDR_SLOT_I2C_DEV,
 	I3C_ADDR_SLOT_I3C_DEV,
 	I3C_ADDR_SLOT_STATUS_MASK = 3,
+	I3C_ADDR_SLOT_EXT_STATUS_MASK = 7,
+	I3C_ADDR_SLOT_EXT_DESIRED = BIT(2),
 };
 
+#define I3C_ADDR_SLOT_STATUS_BITS 4
+
 /**
  * struct i3c_bus - I3C bus object
  * @cur_master: I3C master currently driving the bus. Since I3C is multi-master
@@ -354,7 +360,7 @@ enum i3c_addr_slot_status {
 struct i3c_bus {
 	struct i3c_dev_desc *cur_master;
 	int id;
-	unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG];
+	unsigned long addrslots[((I2C_MAX_ADDR + 1) * I3C_ADDR_SLOT_STATUS_BITS) / BITS_PER_LONG];
 	enum i3c_bus_mode mode;
 	struct {
 		unsigned long i3c;