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| author | Sam Ravnborg <sam@ravnborg.org> | 2008-07-27 23:00:59 +0200 |
|---|---|---|
| committer | Sam Ravnborg <sam@ravnborg.org> | 2008-07-27 23:00:59 +0200 |
| commit | a439fe51a1f8eb087c22dd24d69cebae4a3addac (patch) | |
| tree | e32d1fa97a220ab598d8ab364205817c5bf2bd6f /include/asm-sparc/tsunami.h | |
| parent | 837b41b5de356aa67abb2cadb5eef3efc7776f91 (diff) | |
| download | linux-a439fe51a1f8eb087c22dd24d69cebae4a3addac.tar.gz linux-a439fe51a1f8eb087c22dd24d69cebae4a3addac.tar.bz2 linux-a439fe51a1f8eb087c22dd24d69cebae4a3addac.zip | |
sparc, sparc64: use arch/sparc/include
The majority of this patch was created by the following script:
***
ASM=arch/sparc/include/asm
mkdir -p $ASM
git mv include/asm-sparc64/ftrace.h $ASM
git rm include/asm-sparc64/*
git mv include/asm-sparc/* $ASM
sed -ie 's/asm-sparc64/asm/g' $ASM/*
sed -ie 's/asm-sparc/asm/g' $ASM/*
***
The rest was an update of the top-level Makefile to use sparc
for header files when sparc64 is being build.
And a small fixlet to pick up the correct unistd.h from
sparc64 code.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Diffstat (limited to 'include/asm-sparc/tsunami.h')
| -rw-r--r-- | include/asm-sparc/tsunami.h | 64 |
1 files changed, 0 insertions, 64 deletions
diff --git a/include/asm-sparc/tsunami.h b/include/asm-sparc/tsunami.h deleted file mode 100644 index 5bbd1d523baa..000000000000 --- a/include/asm-sparc/tsunami.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * tsunami.h: Module specific definitions for Tsunami V8 Sparcs - * - * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) - */ - -#ifndef _SPARC_TSUNAMI_H -#define _SPARC_TSUNAMI_H - -#include <asm/asi.h> - -/* The MMU control register on the Tsunami: - * - * ----------------------------------------------------------------------- - * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME| - * ----------------------------------------------------------------------- - * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0 - * - * SW: Enable Software Table Walks 0=off 1=on - * AV: Address View bit - * DV: Data View bit - * MV: Memory View bit - * PC: Parity Control - * ITD: ITBR disable - * ALC: Alternate Cacheable - * PE: Parity Enable 0=off 1=on - * RC: Refresh Control - * IE: Instruction cache Enable 0=off 1=on - * DE: Data cache Enable 0=off 1=on - * NF: No Fault, same as all other SRMMUs - * ME: MMU Enable, same as all other SRMMUs - */ - -#define TSUNAMI_SW 0x00800000 -#define TSUNAMI_AV 0x00400000 -#define TSUNAMI_DV 0x00200000 -#define TSUNAMI_MV 0x00100000 -#define TSUNAMI_PC 0x00020000 -#define TSUNAMI_ITD 0x00010000 -#define TSUNAMI_ALC 0x00008000 -#define TSUNAMI_PE 0x00001000 -#define TSUNAMI_RCMASK 0x00000C00 -#define TSUNAMI_IENAB 0x00000200 -#define TSUNAMI_DENAB 0x00000100 -#define TSUNAMI_NF 0x00000002 -#define TSUNAMI_ME 0x00000001 - -static inline void tsunami_flush_icache(void) -{ - __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" - : /* no outputs */ - : "i" (ASI_M_IC_FLCLEAR) - : "memory"); -} - -static inline void tsunami_flush_dcache(void) -{ - __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" - : /* no outputs */ - : "i" (ASI_M_DC_FLCLEAR) - : "memory"); -} - -#endif /* !(_SPARC_TSUNAMI_H) */ |