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| author | Marek Vasut <marex@denx.de> | 2024-06-25 14:02:33 +0200 |
|---|---|---|
| committer | Robert Foss <rfoss@kernel.org> | 2024-06-27 11:07:07 +0200 |
| commit | 9c433c87e81c2dfc005b72b9fe822b065ffa044e (patch) | |
| tree | f7507fba190fac87554ec6a81d545ddf17eeecf9 /drivers | |
| parent | 3f13e53bcf30583ab804d94973157d515330dd6e (diff) | |
| download | linux-9c433c87e81c2dfc005b72b9fe822b065ffa044e.tar.gz linux-9c433c87e81c2dfc005b72b9fe822b065ffa044e.tar.bz2 linux-9c433c87e81c2dfc005b72b9fe822b065ffa044e.zip | |
drm/bridge: tc358767: Set LSCLK divider for SYSCLK to 1
The only information in the datasheet regarding this divider is a note
in SYS_PLLPARAM register documentation which states that when LSCLK is
270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when
LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test
confirms using LSCLK_DIV 1 has no adverse effects either. In the worst
case, the internal TC358767 clock would run faster.
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240625120334.145320-4-marex@denx.de
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/bridge/tc358767.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 0338b7a7bbef..610df536a6ed 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -738,7 +738,7 @@ static int tc_stream_clock_calc(struct tc_data *tc) static int tc_set_syspllparam(struct tc_data *tc) { unsigned long rate; - u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; + u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1; rate = clk_get_rate(tc->refclk); switch (rate) { |