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| author | Neil Armstrong <narmstrong@baylibre.com> | 2020-11-16 11:16:45 +0100 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2020-11-20 15:23:33 +0530 |
| commit | 450889074f4fafaff0ea82c2c4c7e0a93b3cd5c7 (patch) | |
| tree | 484f20ca3714e520e393306481869c86585726fa /drivers/phy/amlogic | |
| parent | e1404d203139d871946df9091a6e042b1154bd63 (diff) | |
| download | linux-450889074f4fafaff0ea82c2c4c7e0a93b3cd5c7.tar.gz linux-450889074f4fafaff0ea82c2c4c7e0a93b3cd5c7.tar.bz2 linux-450889074f4fafaff0ea82c2c4c7e0a93b3cd5c7.zip | |
dt-bindings: phy: amlogic,meson-axg-mipi-pcie-analog: remove reg attribute
The PHY registers happens to be at the beginning of a large zone containing
interleaved system registers (mainly clocks, power management, PHY control..),
found in all Amlogic SoC so far.
The goal is to model it the same way as the other "features" of this zone,
like Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
and Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
and have a coherent bindings scheme over the Amlogic SoCs.
This update the description, removed the reg attribute then updates the example
accordingly.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201116101647.73448-2-narmstrong@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy/amlogic')
0 files changed, 0 insertions, 0 deletions