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| author | Kevin Xie <kevin.xie@starfivetech.com> | 2024-03-28 17:18:33 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-05-28 11:15:29 -0500 |
| commit | d5ceb9496c565eb5763c127c6eb2d2b3068ab1df (patch) | |
| tree | c48a53f9f58f0d36be19f53072ef926d4f1ff620 /drivers/pci/pci.h | |
| parent | d76ef0531c0794d22eacfb1f0f887590e92fbf8e (diff) | |
| download | linux-d5ceb9496c565eb5763c127c6eb2d2b3068ab1df.tar.gz linux-d5ceb9496c565eb5763c127c6eb2d2b3068ab1df.tar.bz2 linux-d5ceb9496c565eb5763c127c6eb2d2b3068ab1df.zip | |
PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value
Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum
waiting time between exit from a conventional reset and sending the
first configuration request to the device.
As described in PCIe r6.0, sec 6.6.1 <Conventional Reset>, there are two
different use cases of the value:
- "With a Downstream Port that does not support Link speeds greater
than 5.0 GT/s, software must wait a minimum of 100 ms following exit
from a Conventional Reset before sending a Configuration Request to
the device immediately below that Port."
- "With a Downstream Port that supports Link speeds greater than
5.0 GT/s, software must wait a minimum of 100 ms after Link training
completes before sending a Configuration Request to the device
immediately below that Port."
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240328091835.14797-21-minda.chen@starfivetech.com
Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
Diffstat (limited to 'drivers/pci/pci.h')
| -rw-r--r-- | drivers/pci/pci.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index fd44565c4756..a4477594c525 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,21 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * PCIe r6.0, sec 6.6.1 <Conventional Reset> + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; |