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| author | Rick Wertenbroek <rick.wertenbroek@gmail.com> | 2023-04-18 09:46:51 +0200 |
|---|---|---|
| committer | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2023-06-22 09:36:51 +0200 |
| commit | 9dd3c7c4c8c3f7f010d9cdb7c3f42506d93c9527 (patch) | |
| tree | 4d816de930868c6174bcbd3d011492b3b8e0c9b1 /drivers/pci/controller/pcie-rockchip.h | |
| parent | f397fd4ac1fa3afcabd8cee030f953ccaed2a364 (diff) | |
| download | linux-9dd3c7c4c8c3f7f010d9cdb7c3f42506d93c9527.tar.gz linux-9dd3c7c4c8c3f7f010d9cdb7c3f42506d93c9527.tar.bz2 linux-9dd3c7c4c8c3f7f010d9cdb7c3f42506d93c9527.zip | |
PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked
The RK3399 PCIe controller should wait until the PHY PLLs are locked.
Add poll and timeout to wait for PHY PLLs to be locked. If they cannot
be locked generate error message and jump to error handler. Accessing
registers in the PHY clock domain when PLLs are not locked causes hang
The PHY PLLs status is checked through a side channel register.
This is documented in the TRM section 17.5.8.1 "PCIe Initialization
Sequence".
Link: https://lore.kernel.org/r/20230418074700.1083505-5-rick.wertenbroek@gmail.com
Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller")
Tested-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/pci/controller/pcie-rockchip.h')
| -rw-r--r-- | drivers/pci/controller/pcie-rockchip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 51a123e5c0cf..f3a5ff1cf7f4 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -38,6 +38,8 @@ #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) +#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) +#define PCIE_CLIENT_PHY_ST BIT(12) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) #define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 |