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| author | Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2022-11-13 22:12:57 +0300 |
|---|---|---|
| committer | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2022-11-23 16:01:55 +0100 |
| commit | 7f9e982dc4fcf7b4bc7e9dc8a9f344395fc125b8 (patch) | |
| tree | bf32e1937e723189f12ee3074cbc1c8a7185b170 /drivers/pci/controller/dwc/pcie-designware.h | |
| parent | 8522e17d4cab47b35d43943ca13d677e76ab01b7 (diff) | |
| download | linux-7f9e982dc4fcf7b4bc7e9dc8a9f344395fc125b8.tar.gz linux-7f9e982dc4fcf7b4bc7e9dc8a9f344395fc125b8.tar.bz2 linux-7f9e982dc4fcf7b4bc7e9dc8a9f344395fc125b8.zip | |
PCI: dwc: Introduce generic controller capabilities interface
Since in addition to the already available iATU unrolled mapping we are
about to add a few more DW PCIe platform-specific capabilities (CDM-check
and generic clocks/resets resources) let's add a generic interface to set
and get the flags indicating their availability. The new interface shall
improve maintainability of the platform-specific code.
Link: https://lore.kernel.org/r/20221113191301.5526-17-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.h')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 37801bbce854..c6dddacee3b1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -12,6 +12,7 @@ #define _PCIE_DESIGNWARE_H #include <linux/bitfield.h> +#include <linux/bitops.h> #include <linux/dma-mapping.h> #include <linux/irq.h> #include <linux/msi.h> @@ -43,6 +44,15 @@ (__dw_pcie_ver_cmp(_pci, _ver, ==) && \ __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, >=)) +/* DWC PCIe controller capabilities */ +#define DW_PCIE_CAP_IATU_UNROLL 1 + +#define dw_pcie_cap_is(_pci, _cap) \ + test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) + +#define dw_pcie_cap_set(_pci, _cap) \ + set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) + /* Parameters for the waiting for link up routine */ #define LINK_WAIT_MAX_RETRIES 10 #define LINK_WAIT_USLEEP_MIN 90000 @@ -317,10 +327,10 @@ struct dw_pcie { const struct dw_pcie_ops *ops; u32 version; u32 type; + unsigned long caps; int num_lanes; int link_gen; u8 n_fts[2]; - bool iatu_unroll_enabled: 1; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) |