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| author | Alok Prasad <palok@marvell.com> | 2021-08-24 04:02:46 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-08-25 10:38:16 +0100 |
| commit | 755f905340802e2efb1ea96b9ce0f442916c2645 (patch) | |
| tree | 85c81ecc0af1e1dfe9032590727cf0fcf63d4af5 /drivers/net/ethernet/qlogic/qed/qed_int.c | |
| parent | 406f42fa0d3cbcea3766c3111d79ac5afe711c5b (diff) | |
| download | linux-755f905340802e2efb1ea96b9ce0f442916c2645.tar.gz linux-755f905340802e2efb1ea96b9ce0f442916c2645.tar.bz2 linux-755f905340802e2efb1ea96b9ce0f442916c2645.zip | |
qed: Enable automatic recovery on error condition.
This patch enables automatic recovery by default in case of various
error condition like fw assert , hardware error etc.
This also ensure driver can handle multiple iteration of assertion
conditions.
Signed-off-by: Ariel Elior <aelior@marvell.com>
Signed-off-by: Shai Malin <smalin@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Alok Prasad <palok@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qed/qed_int.c')
| -rw-r--r-- | drivers/net/ethernet/qlogic/qed/qed_int.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/net/ethernet/qlogic/qed/qed_int.c b/drivers/net/ethernet/qlogic/qed/qed_int.c index ab6d4f737316..f78e6055f654 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_int.c +++ b/drivers/net/ethernet/qlogic/qed/qed_int.c @@ -351,6 +351,9 @@ static int qed_fw_assertion(struct qed_hwfn *p_hwfn) qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT, "FW assertion!\n"); + /* Clear assert indications */ + qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MISC_REG_AEU_GENERAL_ATTN_32, 0); + return -EINVAL; } @@ -953,6 +956,13 @@ qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", p_bit_name); + /* Re-enable FW aassertion (Gen 32) interrupts */ + val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, + MISC_REG_AEU_ENABLE4_IGU_OUT_0); + val |= MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32; + qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, + MISC_REG_AEU_ENABLE4_IGU_OUT_0, val); + out: return rc; } |