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| author | Brett Creeley <brett.creeley@intel.com> | 2019-06-26 02:20:15 -0700 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2019-07-31 10:23:04 -0700 |
| commit | c31a5c25bb19c62d1cea69d3abcc7e0405bd4596 (patch) | |
| tree | 7e49e09eb64209b2bd09ef384b767f86f4a392bc /drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h | |
| parent | 17bc6d07212c8bc4521056a7f871d143192d385c (diff) | |
| download | linux-c31a5c25bb19c62d1cea69d3abcc7e0405bd4596.tar.gz linux-c31a5c25bb19c62d1cea69d3abcc7e0405bd4596.tar.bz2 linux-c31a5c25bb19c62d1cea69d3abcc7e0405bd4596.zip | |
ice: Always set prefena when configuring an Rx queue
Currently we are always setting prefena to 0. This is causing the
hardware to only fetch descriptors when there are none free in the cache
for a received packet instead of prefetching when it has used the last
descriptor regardless of incoming packets. Fix this by allowing the
hardware to prefetch Rx descriptors.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h')
| -rw-r--r-- | drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h b/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h index 510a8c900e61..57ea6811fe2c 100644 --- a/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h +++ b/drivers/net/ethernet/intel/ice/ice_lan_tx_rx.h @@ -290,6 +290,7 @@ struct ice_rlan_ctx { u8 tphdata_ena; u8 tphhead_ena; u16 lrxqthresh; /* bigger than needed, see above for reason */ + u8 prefena; /* NOTE: normally must be set to 1 at init */ }; struct ice_ctx_ele { |