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| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2018-06-19 14:23:21 +0300 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2018-07-03 23:05:35 +0200 |
| commit | 3bd4f277274bd7dde65879e5c8cd16d0b34eba90 (patch) | |
| tree | ab00e44111170c8f833ccb0144496c4dfbdfab72 /drivers/i2c/busses/i2c-designware-common.c | |
| parent | 83b2cb48cbc5c4196fcc9357836f30713f74dbc2 (diff) | |
| download | linux-3bd4f277274bd7dde65879e5c8cd16d0b34eba90.tar.gz linux-3bd4f277274bd7dde65879e5c8cd16d0b34eba90.tar.bz2 linux-3bd4f277274bd7dde65879e5c8cd16d0b34eba90.zip | |
i2c: designware: Call i2c_dw_clk_rate() only once in i2c_dw_init_master()
This is rather readability update than micro-optimization, or if not
optimization at all. We take the input clock rate to a variable and pass
that to SCL timing parameter calculation functions.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c/busses/i2c-designware-common.c')
0 files changed, 0 insertions, 0 deletions