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| author | Dillon Varone <Dillon.Varone@amd.com> | 2022-12-21 20:28:56 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-01-17 15:41:11 -0500 |
| commit | e36193123f3f5e4ac837f32daa78125d8e9d749b (patch) | |
| tree | 19ecb455143b218595d76ec2f45152012dcb5c74 /drivers/gpu | |
| parent | 2ebd1036209c2e7b61e6bc6e5bee4b67c1684ac6 (diff) | |
| download | linux-e36193123f3f5e4ac837f32daa78125d8e9d749b.tar.gz linux-e36193123f3f5e4ac837f32daa78125d8e9d749b.tar.bz2 linux-e36193123f3f5e4ac837f32daa78125d8e9d749b.zip | |
drm/amd/display: Account for MPO planes in dcn32 mall alloc calculations
[WHY?]
Cannot only consider the MALL required from top pipes because of the MPO
case.
[HOW?]
Only count a pipe if it fits the following criteria:
1) does not have a top pipe (is the topmost pipe for that plane)
2) it does have a top pipe, but that pipe is associated with a different
plane
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c index 5b928f3b719d..7feb8759e475 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c @@ -1356,9 +1356,10 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, context->res_ctx.pipe_ctx[i].surface_size_in_mall_bytes = get_surface_size_in_mall(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); /* MALL Allocation Sizes */ - /* count from active, top pipes only */ + /* count from active, top pipes per plane only */ if (context->res_ctx.pipe_ctx[i].stream && context->res_ctx.pipe_ctx[i].plane_state && - context->res_ctx.pipe_ctx[i].top_pipe == NULL && + (context->res_ctx.pipe_ctx[i].top_pipe == NULL || + context->res_ctx.pipe_ctx[i].plane_state != context->res_ctx.pipe_ctx[i].top_pipe->plane_state) && context->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) { /* SS: all active surfaces stored in MALL */ if (context->res_ctx.pipe_ctx[i].stream->mall_stream_config.type != SUBVP_PHANTOM) { |