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| author | Aric Cyr <aric.cyr@amd.com> | 2020-07-27 21:21:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-08-10 18:08:36 -0400 |
| commit | a49f6727e14caff32419cc3002b9ae9cafb750d7 (patch) | |
| tree | d82b0b453629ccfe7b9c03cef2597cf7fedbe086 /drivers/gpu | |
| parent | 97a9b60fa3bf29d29d0fc253a98096c02fb8106e (diff) | |
| download | linux-a49f6727e14caff32419cc3002b9ae9cafb750d7.tar.gz linux-a49f6727e14caff32419cc3002b9ae9cafb750d7.tar.bz2 linux-a49f6727e14caff32419cc3002b9ae9cafb750d7.zip | |
drm/amd/display: Fix incorrect backlight register offset for DCN
[Why]
Typo in backlight refactor inctroduced wrong register offset.
[How]
Change DCE to DCN register map for PWRSEQ_REF_DIV
Cc: stable@vger.kernel.org
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Ashley Thomas <Ashley.Thomas2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h index 70ec691e14d2..99c68ca9c7e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h @@ -49,7 +49,7 @@ #define DCN_PANEL_CNTL_REG_LIST()\ DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \ DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \ - DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \ + DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \ SR(BL_PWM_CNTL), \ SR(BL_PWM_CNTL2), \ SR(BL_PWM_PERIOD_CNTL), \ |