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| author | Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> | 2017-03-31 14:15:31 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:22:35 -0400 |
| commit | 9faa423716b17b0c9ba92fd12737968de6918d88 (patch) | |
| tree | 2788da3c78350c82b1472f363220560160563a9e /drivers/gpu | |
| parent | 7160c74cd00bc0a5f143c24096e1a45c51f3d202 (diff) | |
| download | linux-9faa423716b17b0c9ba92fd12737968de6918d88.tar.gz linux-9faa423716b17b0c9ba92fd12737968de6918d88.tar.bz2 linux-9faa423716b17b0c9ba92fd12737968de6918d88.zip | |
drm/amd/display: Fix s3 hang on resume.
Avoid enabling CRTC_VERTICAL_INTERRUPT0 twice on resume.
It's enabled once from within manage_dm_interrupts in mode set
and another explicitly from amdgpu_dm_irq_resume_late.
Seems it lead to CRTC hang.
Signed-off-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h | 2 |
3 files changed, 13 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1077af91884f..30148b4eabae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -575,7 +575,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); - amdgpu_dm_irq_resume(adev); + amdgpu_dm_irq_resume_late(adev); return ret; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 682e9c3ad8e5..4aee146a848f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -504,8 +504,11 @@ int amdgpu_dm_irq_suspend( DRM_DEBUG_KMS("DM_IRQ: suspend\n"); - /* disable HW interrupt */ - for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) { + /** + * Disable HW interrupt for HPD and HPDRX only since FLIP and VBLANK + * will be disabled from manage_dm_interrupts on disable CRTC. + */ + for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6RX; src++) { hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head; hnd_list_h = &adev->dm.irq_handler_list_high_tab[src]; if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h)) @@ -544,7 +547,7 @@ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev) return 0; } -int amdgpu_dm_irq_resume(struct amdgpu_device *adev) +int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev) { int src; struct list_head *hnd_list_h, *hnd_list_l; @@ -554,8 +557,11 @@ int amdgpu_dm_irq_resume(struct amdgpu_device *adev) DRM_DEBUG_KMS("DM_IRQ: resume\n"); - /* re-enable HW interrupt */ - for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) { + /** + * Renable HW interrupt for HPD and only since FLIP and VBLANK + * will be enabled from manage_dm_interrupts on enable CRTC. + */ + for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6; src++) { hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head; hnd_list_h = &adev->dm.irq_handler_list_high_tab[src]; if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h)) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h index 9339861c8897..9d3007634266 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h @@ -117,6 +117,6 @@ int amdgpu_dm_irq_suspend(struct amdgpu_device *adev); * */ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev); -int amdgpu_dm_irq_resume(struct amdgpu_device *adev); +int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev); #endif /* __AMDGPU_DM_IRQ_H__ */ |