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authorRodrigo Vivi <rodrigo.vivi@intel.com>2022-12-30 04:09:09 -0500
committerRodrigo Vivi <rodrigo.vivi@intel.com>2022-12-30 04:18:36 -0500
commitb501d4dc83aa3940189b68045cadc8b3eac73988 (patch)
treee5310a4fafd59505c3db86bb05baf964cb8da944 /drivers/gpu/host1x/dev.c
parent4071d98b296a5bc5fd4b15ec651bd05800ec9510 (diff)
parent1b929c02afd37871d5afb9d498426f83432e71c2 (diff)
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Merge drm/drm-next into drm-intel-gt-next
Sync after v6.2-rc1 landed in drm-next. We need to get some dependencies in place before we can merge the fixes series from Gwan-gyeong and Chris. References: https://lore.kernel.org/all/Y6x5JCDnh2rvh4lA@intel.com/ Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/host1x/dev.c')
-rw-r--r--drivers/gpu/host1x/dev.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 0cd3f97e7e49..f31039aca03c 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -225,6 +225,18 @@ static const struct host1x_sid_entry tegra234_sid_table[] = {
.offset = 0x34,
.limit = 0x34
},
+ {
+ /* NVDEC channel */
+ .base = 0x17c8,
+ .offset = 0x30,
+ .limit = 0x30,
+ },
+ {
+ /* NVDEC MMIO */
+ .base = 0x1698,
+ .offset = 0x34,
+ .limit = 0x34,
+ },
};
static const struct host1x_info host1x08_info = {
@@ -292,6 +304,10 @@ static void host1x_setup_virtualization_tables(struct host1x *host)
static bool host1x_wants_iommu(struct host1x *host1x)
{
+ /* Our IOMMU usage policy doesn't currently play well with GART */
+ if (of_machine_is_compatible("nvidia,tegra20"))
+ return false;
+
/*
* If we support addressing a maximum of 32 bits of physical memory
* and if the host1x firewall is enabled, there's no need to enable