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| author | Jaehyun Chung <jaehyun.chung@amd.com> | 2019-07-15 17:35:56 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-15 10:53:49 -0500 |
| commit | 37495fbdf12d1bce30dbc228c901ef45eba35739 (patch) | |
| tree | d76f2f4dfe33d94252c537e5295f831307215d49 /drivers/gpu/drm | |
| parent | f7f38ffef56b0138f902efd261a6d90680fec2d3 (diff) | |
| download | linux-37495fbdf12d1bce30dbc228c901ef45eba35739.tar.gz linux-37495fbdf12d1bce30dbc228c901ef45eba35739.tar.bz2 linux-37495fbdf12d1bce30dbc228c901ef45eba35739.zip | |
drm/amd/display: Add work-around option to skip DCN20 clock updates
[Why] Auto Overclock Memory fails for some systems that don't support
p-state.
[How] Implement the workaround, and it's corresponding enable flag.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 24775ab81216..3e8ac303bd52 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -198,6 +198,9 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, bool force_reset = false; int i; + if (dc->work_arounds.skip_clock_update) + return; + if (clk_mgr_base->clks.dispclk_khz == 0 || dc->debug.force_clock_mode & 0x1) { //this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e3d7710b5c54..1866fa71a764 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -122,6 +122,7 @@ struct dc_bug_wa { bool no_connect_phy_config; bool dedcn20_305_wa; struct display_mode_lib alternate_dml; + bool skip_clock_update; }; #endif |