Merge tag 'for-v3.11-rc/omap-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.12/cleanup

This series removes the currently-unused PRCM macros from
arch/arm/mach-omap2.

Basic test logs are available at:

http://www.pwsan.com/omap/testlogs/drop_unused_prcm_macros_v3.11-rc/20130721211401/

Once, years ago, we thought that it would be good to document the PRCM
register bits in the Linux codebase.  Most folks in the broader
community did not have access to the same documentation, so we thought
that they might be able to use these bits to fix bugs and improve the
code.

We were also able to autogenerate most of these macros, so it was
thought that defining them in advance would reduce the risk of error,
inconsistencies, and merge conflicts caused when patch sets
incrementally defined them by hand.

Well, nice thoughts.  But the first rationale was rendered partially
obsolete when TI started to release public TRM documentation PDFs at
some point in the OMAP3 timeframe.  (Despite their weaknesses, TI's
public OMAP TRMs remain the most useful public documentation available
for any ARM Linux SoC -- at least to the extent of my knowledge.)  And
then the current Linux development tropism towards
development-by-negative-diffstat obliterated the remainder of the
above two philosophies.

So, for the few, the masochistic, out there who wish to continue
developing TI PRCM code, I would ask that you resurrect any
additionally-needed macros from these commits, rather than writing
them manually.  Purely for the sake of a pleasant atavism, perhaps; the
way one appreciates a used bookstore, or a video rental store...

And thanks to the upstream maintainers for being patient while we
adjust.

1 files changed, 11 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e49059dc9b8f..038dcac7670c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -139,6 +139,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
 void evergreen_program_aspm(struct radeon_device *rdev);
 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
 				     int ring, u32 cp_int_cntl);
+extern void cayman_vm_decode_fault(struct radeon_device *rdev,
+				   u32 status, u32 addr);
 
 static const u32 evergreen_golden_registers[] =
 {
@@ -4586,6 +4588,7 @@ int evergreen_irq_process(struct radeon_device *rdev)
 	bool queue_hotplug = false;
 	bool queue_hdmi = false;
 	bool queue_thermal = false;
+	u32 status, addr;
 
 	if (!rdev->ih.enabled || rdev->shutdown)
 		return IRQ_NONE;
@@ -4872,11 +4875,14 @@ restart_ih:
 			break;
 		case 146:
 		case 147:
+			addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
+			status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
 			dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
 			dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
-				RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
+				addr);
 			dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
-				RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
+				status);
+			cayman_vm_decode_fault(rdev, status, addr);
 			/* reset addr and status */
 			WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
 			break;
@@ -5509,6 +5515,9 @@ void evergreen_program_aspm(struct radeon_device *rdev)
 	 */
 	bool fusion_platform = false;
 
+	if (radeon_aspm == 0)
+		return;
+
 	if (!(rdev->flags & RADEON_IS_PCIE))
 		return;