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authorMatt Roper <matthew.d.roper@intel.com>2023-03-27 21:55:46 +0200
committerAndi Shyti <andi.shyti@linux.intel.com>2023-03-28 11:22:05 +0200
commitde4149730d9d72f50d4e6dfedad0d11b1df05b7e (patch)
treed0a16e29e2e2752a80374c4368c002ea22f69bd2 /drivers/gpu/drm/i915/intel_uncore.c
parent5dff5d092ba6c5485aac1467dad938c74ba6ed57 (diff)
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drm/i915: Sanitycheck MMIO access early in driver load
We occasionally see the PCI device in a non-accessible state at the point the driver is loaded. When this happens, all BAR accesses will read back as 0xFFFFFFFF. Rather than reading registers and misinterpreting their (invalid) values, let's specifically check for 0xFFFFFFFF in a register that cannot have that value to see if the device is accessible. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230327195547.356584-2-andi.shyti@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_uncore.c')
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c34
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 7894447c2858..67f57dde8672 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2602,11 +2602,45 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
return 0;
}
+static int sanity_check_mmio_access(struct intel_uncore *uncore)
+{
+ struct drm_i915_private *i915 = uncore->i915;
+
+ if (GRAPHICS_VER(i915) < 8)
+ return 0;
+
+ /*
+ * Sanitycheck that MMIO access to the device is working properly. If
+ * the CPU is unable to communcate with a PCI device, BAR reads will
+ * return 0xFFFFFFFF. Let's make sure the device isn't in this state
+ * before we start trying to access registers.
+ *
+ * We use the primary GT's forcewake register as our guinea pig since
+ * it's been around since HSW and it's a masked register so the upper
+ * 16 bits can never read back as 1's if device access is operating
+ * properly.
+ *
+ * If MMIO isn't working, we'll wait up to 2 seconds to see if it
+ * recovers, then give up.
+ */
+#define COND (__raw_uncore_read32(uncore, FORCEWAKE_MT) != ~0)
+ if (wait_for(COND, 2000) == -ETIMEDOUT) {
+ drm_err(&i915->drm, "Device is non-operational; MMIO access returns 0xFFFFFFFF!\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+
int intel_uncore_init_mmio(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
int ret;
+ ret = sanity_check_mmio_access(uncore);
+ if (ret)
+ return ret;
+
/*
* The boot firmware initializes local memory and assesses its health.
* If memory training fails, the punit will have been instructed to