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| author | Maxime Ripard <mripard@kernel.org> | 2024-01-22 09:44:15 +0100 |
|---|---|---|
| committer | Maxime Ripard <mripard@kernel.org> | 2024-01-22 09:44:15 +0100 |
| commit | cf79f291f985662150363b4a93d16f88f12643bc (patch) | |
| tree | a803f6e9b1e34f100783538955b9ce34628cd5dd /drivers/gpu/drm/i915/gt/intel_engine_regs.h | |
| parent | a20f1b02bafcbf5a32d96a1d4185d6981cf7d016 (diff) | |
| parent | 6613476e225e090cc9aad49be7fa504e290dd33d (diff) | |
| download | linux-cf79f291f985662150363b4a93d16f88f12643bc.tar.gz linux-cf79f291f985662150363b4a93d16f88f12643bc.tar.bz2 linux-cf79f291f985662150363b4a93d16f88f12643bc.zip | |
Merge v6.8-rc1 into drm-misc-fixes
Let's kickstart the 6.8 fix cycle.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_engine_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine_regs.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h b/drivers/gpu/drm/i915/gt/intel_engine_regs.h index fdd4ddd3a978..a8eac59e3779 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h @@ -118,9 +118,15 @@ #define CCID_EXTENDED_STATE_RESTORE BIT(2) #define CCID_EXTENDED_STATE_SAVE BIT(3) #define RING_BB_PER_CTX_PTR(base) _MMIO((base) + 0x1c0) /* gen8+ */ +#define PER_CTX_BB_FORCE BIT(2) +#define PER_CTX_BB_VALID BIT(0) + #define RING_INDIRECT_CTX(base) _MMIO((base) + 0x1c4) /* gen8+ */ #define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base) + 0x1c8) /* gen8+ */ #define ECOSKPD(base) _MMIO((base) + 0x1d0) +#define XEHP_BLITTER_SCHEDULING_MODE_MASK REG_GENMASK(12, 11) +#define XEHP_BLITTER_ROUND_ROBIN_MODE \ + REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1) #define ECO_CONSTANT_BUFFER_SR_DISABLE REG_BIT(4) #define ECO_GATING_CX_ONLY REG_BIT(3) #define GEN6_BLITTER_FBC_NOTIFY REG_BIT(3) @@ -257,5 +263,7 @@ #define VDBOX_CGCTL3F18(base) _MMIO((base) + 0x3f18) #define ALNUNIT_CLKGATE_DIS REG_BIT(13) +#define VDBOX_CGCTL3F1C(base) _MMIO((base) + 0x3f1c) +#define MFXPIPE_CLKGATE_DIS REG_BIT(3) #endif /* __INTEL_ENGINE_REGS__ */ |