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| author | Andi Shyti <andi.shyti@linux.intel.com> | 2022-12-01 00:58:01 +0100 |
|---|---|---|
| committer | Andi Shyti <andi.shyti@linux.intel.com> | 2022-12-06 10:52:41 +0100 |
| commit | 09f9b4418e417b6452d1bcd7a9544a68fc1e59d5 (patch) | |
| tree | 6ccdd48748ef6c98bf1adc8f7ea58e74dfe225e9 /drivers/gpu/drm/i915/display | |
| parent | f2053d346615f2c6bb4c0663276274b2da3f6871 (diff) | |
| download | linux-09f9b4418e417b6452d1bcd7a9544a68fc1e59d5.tar.gz linux-09f9b4418e417b6452d1bcd7a9544a68fc1e59d5.tar.bz2 linux-09f9b4418e417b6452d1bcd7a9544a68fc1e59d5.zip | |
drm/i915: Limit the display memory alignment to 32 bit instead of 64
The coming commit "drm/i915: Introduce guard pages to i915_vma"
from Chris, was originally changing display_alignment to u32
from u64. The reason is that the display GGTT is and will be
limited o 4GB.
Put it in a separate patch and use "max(...)" instead of
"max_t(64, ...)" when asigning the value. We can safely use max
as we know beforehand that the comparison is between two u32
variables.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221130235805.221010-2-andi.shyti@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 6900acbb1381..1aca7552a85d 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -91,7 +91,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, goto err; } - vma->display_alignment = max_t(u64, vma->display_alignment, alignment); + vma->display_alignment = max(vma->display_alignment, alignment); i915_gem_object_flush_if_display(obj); |