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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-05-16 16:56:13 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-05-22 15:45:34 +0300 |
| commit | 04c09e4b879b225f3747606bcfc97d00d82d800f (patch) | |
| tree | 5e2881342b999c1a97a09f1756b9ac307cd282a7 /drivers/gpu/drm/i915/display/intel_psr.c | |
| parent | 199bc8c175d712be1610dcad7f7240ad5c864281 (diff) | |
| download | linux-04c09e4b879b225f3747606bcfc97d00d82d800f.tar.gz linux-04c09e4b879b225f3747606bcfc97d00d82d800f.tar.bz2 linux-04c09e4b879b225f3747606bcfc97d00d82d800f.zip | |
drm/i915: Simplify PIPESRC_ERLY_TPT definition
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
of _MMIO_PIPE2().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d18baeb971bb..f59238d3d484 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2384,7 +2384,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st if (!crtc_state->enable_psr2_su_region_et) return; - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe), + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), crtc_state->pipe_srcsz_early_tpt); } |