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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-04-22 11:34:54 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-04-30 21:13:29 +0300 |
| commit | 61f73e8c5c46ba1d981f6a0ea49748559e1325f6 (patch) | |
| tree | e37798bcae51d2f10dc36dd411710a49950a961a /drivers/gpu/drm/i915/display/intel_dpio_phy.c | |
| parent | 263ed349388e2cbe02ce45be7d9079c96ad21b87 (diff) | |
| download | linux-61f73e8c5c46ba1d981f6a0ea49748559e1325f6.tar.gz linux-61f73e8c5c46ba1d981f6a0ea49748559e1325f6.tar.bz2 linux-61f73e8c5c46ba1d981f6a0ea49748559e1325f6.zip | |
drm/i915/dpio: Rename a few CHV DPIO PHY registers
Drop the leading underscore from the CHV PHY common lane
register definitions. We use these directly from actual
code so the underscore here is misleading as usually it indicates
an intermediate define that shouldn't be used directly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240422083457.23815-12-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpio_phy.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpio_phy.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 791902ba729c..89a51b420075 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -883,21 +883,21 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, /* program left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA1_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA1_FORCE; - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA2_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA2_FORCE; - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); } /* program clock channel usage */ @@ -1036,13 +1036,13 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder, /* disable left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); } vlv_dpio_put(dev_priv); |