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| author | Imre Deak <imre.deak@intel.com> | 2023-04-14 20:38:00 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2023-04-19 14:49:16 +0300 |
| commit | 27ac123b454417ea92d77c13a5d94655f53b759c (patch) | |
| tree | dc0ba49f223857fa08d029a122d26fbbee78264e /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | a823c5a825cf9e49b2e20011cd87d93f949c2a27 (diff) | |
| download | linux-27ac123b454417ea92d77c13a5d94655f53b759c.tar.gz linux-27ac123b454417ea92d77c13a5d94655f53b759c.tar.bz2 linux-27ac123b454417ea92d77c13a5d94655f53b759c.zip | |
drm/i915/dp_mst: Fix active port PLL selection for secondary MST streams
The port PLL selection needs to be up-to-date in the CRTC state of both
the primary and all secondary MST streams. The commit removing the
encoder update_prepare/complete hooks (see Fixes: below), stopped doing
this for secondary streams, fix this up.
Fixes: 0f752b2178c9 ("drm/i915: Remove the encoder update_prepare()/complete() hooks")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8336
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230414173800.590790-1-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a88b852c437c..2c49d9ab86a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -674,6 +674,13 @@ static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, if (intel_dp->active_mst_links == 0) dig_port->base.pre_pll_enable(state, &dig_port->base, pipe_config, NULL); + else + /* + * The port PLL state needs to get updated for secondary + * streams as for the primary stream. + */ + intel_ddi_update_active_dpll(state, &dig_port->base, + to_intel_crtc(pipe_config->uapi.crtc)); } static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, |