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| author | Imre Deak <imre.deak@intel.com> | 2024-07-08 22:00:26 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2024-07-11 21:12:06 +0300 |
| commit | 4613aa66e42ba1b0c896495a207b3b26e94e44d5 (patch) | |
| tree | 993b809537c9413540d836bce76d78f79ace3f20 /drivers/gpu/drm/i915/display/intel_dp_link_training.c | |
| parent | 211ad49cf8ccfdc798a719b4d1e000d0a8a9e588 (diff) | |
| download | linux-4613aa66e42ba1b0c896495a207b3b26e94e44d5.tar.gz linux-4613aa66e42ba1b0c896495a207b3b26e94e44d5.tar.bz2 linux-4613aa66e42ba1b0c896495a207b3b26e94e44d5.zip | |
drm/i915/dp: Reset cached LTTPR count if number of LTTPRs is unsupported
After detection the cached LTTPR count can be checked to determine if
LTTPRs in non-transparent mode were detected. Reset the cached LTTPR
count if the reported number of LTTPRs is invalid to ensure the above
checks work as expected.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240708190029.271247-4-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_link_training.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index d044c8e36bb3..56b9c5cb1254 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -174,7 +174,7 @@ static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_ * still taking into account any LTTPR common lane- rate/count limits. */ if (lttpr_count < 0) - return 0; + goto out_reset_lttpr_count; if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { lt_dbg(intel_dp, DP_PHY_DPRX, |