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authorSai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>2024-10-15 13:35:03 +0530
committerRodrigo Vivi <rodrigo.vivi@intel.com>2024-10-17 15:01:05 -0400
commitefa3a5f4f3140423d9087dda0b6b7e999d1effae (patch)
treed5bcfcbf4718192e18d2b861425c50287292a354 /drivers/gpu/drm/i915/display/intel_display_irq.c
parent341e4023032fba6c02326bfc6babd63ef4039712 (diff)
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drm/i915: Remove unused underrun irq/reporting bits
Underrun recovery was defeatured and was never brought into usage. Thus we can remove the underrun recovery interrupt/reporting register bits and related logic introduced to detect/report soft, hard, port underruns. Essentially this is a revert of the commit 8bcc0840cf7c ("drm/i915/xelpd: Enhanced pipe underrun reporting") which originally added this functionality. Also note that PIPE_STATUS_UNDERRUN bit in PIPESTATUS still stays relevant but we would move back to not clearing this sticky bit as we are not using any information from this register. v2: Extend commit message to add more details (Matt Roper) v3: Fix the old commit mention in commit message Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241015080503.3521063-1-sai.teja.pottumuttu@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_irq.c')
-rw-r--r--drivers/gpu/drm/i915/display/intel_display_irq.c19
1 files changed, 3 insertions, 16 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 6197a4bcac4a..a4f42ed3f21a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1021,17 +1021,6 @@ static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
return GEN8_PIPE_PRIMARY_FLIP_DONE;
}
-u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)
-{
- u32 mask = GEN8_PIPE_FIFO_UNDERRUN;
-
- if (DISPLAY_VER(dev_priv) >= 13)
- mask |= XELPD_PIPE_SOFT_UNDERRUN |
- XELPD_PIPE_HARD_UNDERRUN;
-
- return mask;
-}
-
static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_iir, u32 *pica_iir)
{
u32 pica_ier = 0;
@@ -1177,7 +1166,7 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
hsw_pipe_crc_irq_handler(dev_priv, pipe);
- if (iir & gen8_de_pipe_underrun_mask(dev_priv))
+ if (iir & GEN8_PIPE_FIFO_UNDERRUN)
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
@@ -1617,8 +1606,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u8 pipe_mask)
{
struct intel_uncore *uncore = &dev_priv->uncore;
- u32 extra_ier = GEN8_PIPE_VBLANK |
- gen8_de_pipe_underrun_mask(dev_priv) |
+ u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
gen8_de_pipe_flip_done_mask(dev_priv);
enum pipe pipe;
@@ -1807,8 +1795,7 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
GEN12_DSB_INT(INTEL_DSB_2);
de_pipe_enables = de_pipe_masked |
- GEN8_PIPE_VBLANK |
- gen8_de_pipe_underrun_mask(dev_priv) |
+ GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
gen8_de_pipe_flip_done_mask(dev_priv);
de_port_enables = de_port_masked;