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| author | Qingqing Zhuo <qingqing.zhuo@amd.com> | 2021-08-17 16:29:07 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-09-14 15:57:10 -0400 |
| commit | 2a50edbf10c8c56e930bfb53d8f9f00a33fd837e (patch) | |
| tree | 99f27ae2ace3521ac8e31b8a55bd61d3ed1d50dc /drivers/gpu/drm/drm_modes.c | |
| parent | d020970959169627d59a711769f8c4b87bf5f90c (diff) | |
| download | linux-2a50edbf10c8c56e930bfb53d8f9f00a33fd837e.tar.gz linux-2a50edbf10c8c56e930bfb53d8f9f00a33fd837e.tar.bz2 linux-2a50edbf10c8c56e930bfb53d8f9f00a33fd837e.zip | |
drm/amd/display: Apply w/a for hard hang on HPD
[Why]
HPD disable and enable sequences are not mutually exclusive
on Linux. For HPDs that spans under 1s (i.e. HPD low = 1s),
part of the disable sequence (specifically, a request to SMU
to lower refclk) could come right before the call to PHY
enablement, causing DMUB to access an irresponsive PHY
and thus a hard hang on the system.
[How]
Disable 48mhz refclk off when there is any HPD status in
connected state.
Reviewed-by: Hersen Wu <hersenwu@amd.com>
Acked-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/drm_modes.c')
0 files changed, 0 insertions, 0 deletions