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authorAurabindo Pillai <aurabindo.pillai@amd.com>2023-03-21 11:31:22 -0400
committerAlex Deucher <alexander.deucher@amd.com>2023-04-24 18:36:46 -0400
commit7a1187eab0111ac52ec216f2c18cb7822fec4a4c (patch)
tree3ac8685d7088796da6a51b8fdbe47a52322c8b9e /drivers/gpu/drm/amd/display
parent5e9252d8415f50095c854c85cf9ebcc894e9ac0d (diff)
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drm/amd/display: Program OTG vtotal min/max selectors unconditionally
OTG_V_TOTAL_MIN/MAX_SEL bits are required to be programmed to 1 if writes to OTG timing registers need to be honoured. This is usually needed only when freesync is active. However, SubVP + DRR requires that we're able to change timing even without freesync being active (but supported). By unconditionally writing this bit to 1, we remove an unnecessary dependency so that DMCUB can change OTG timing whenever it wants. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c11
1 files changed, 2 insertions, 9 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index 2ee798965bc2..6ef56fb32131 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -245,16 +245,9 @@ static void optc32_set_drr(
}
optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
- optc32_setup_manual_trigger(optc);
- } else {
- REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
- OTG_SET_V_TOTAL_MIN_MASK, 0,
- OTG_V_TOTAL_MIN_SEL, 0,
- OTG_V_TOTAL_MAX_SEL, 0,
- OTG_FORCE_LOCK_ON_EVENT, 0);
-
- optc->funcs->set_vtotal_min_max(optc, 0, 0);
}
+
+ optc32_setup_manual_trigger(optc);
}
static struct timing_generator_funcs dcn32_tg_funcs = {