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| author | Jaehyun Chung <jaehyun.chung@amd.com> | 2019-08-19 16:45:05 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-09-13 18:03:06 -0500 |
| commit | 785908cf19c9eb4803f6bf9c0a7447dc3661d5c3 (patch) | |
| tree | d8fe2db7d24c43add6b869ee2d005952a46a3f4c /drivers/gpu/drm/amd/display | |
| parent | 119630061e72e6512ee8911b473cfacb6b211c53 (diff) | |
| download | linux-785908cf19c9eb4803f6bf9c0a7447dc3661d5c3.tar.gz linux-785908cf19c9eb4803f6bf9c0a7447dc3661d5c3.tar.bz2 linux-785908cf19c9eb4803f6bf9c0a7447dc3661d5c3.zip | |
drm/amd/display: OTC underflow fix
[Why] Underflow occurs on some display setups(repro'd on 3x4K HDR) on boot,
mode set, and hot-plugs with. Underflow occurs because mem clk
is not set high after disabling pstate switching. This behaviour occurs
because some calculations assumed displays were synchronized.
[How] Add a condition to check if timing sync is disabled so that
synchronized vblank can be set to false.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 5a9d3c85eaaa..630f6a7be0ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -1759,7 +1759,7 @@ int dcn20_populate_dml_pipes_from_context( pipe_cnt = i; continue; } - if (!resource_are_streams_timing_synchronizable( + if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable( res_ctx->pipe_ctx[pipe_cnt].stream, res_ctx->pipe_ctx[i].stream)) { synchronized_vblank = false; |