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| author | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2023-04-11 15:43:45 +0300 |
|---|---|---|
| committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2023-04-11 15:43:45 +0300 |
| commit | ea68a3e9d14e9e0bf017d178fb4bd53b6deb1482 (patch) | |
| tree | 4ca0e37218ecc0844d330cb37b956d5219bb1d32 /drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | |
| parent | 16fc9c08f0ec7b1c95f1ea4a16097acdb3fc943d (diff) | |
| parent | 55bf14961db9da61220e6f04bc9919c94b1a6585 (diff) | |
| download | linux-ea68a3e9d14e9e0bf017d178fb4bd53b6deb1482.tar.gz linux-ea68a3e9d14e9e0bf017d178fb4bd53b6deb1482.tar.bz2 linux-ea68a3e9d14e9e0bf017d178fb4bd53b6deb1482.zip | |
Merge drm/drm-next into drm-intel-gt-next
Need to pull in commit from drm-next (earlier in drm-intel-next):
1eca0778f4b3 ("drm/i915: add struct i915_dsm to wrap dsm members together")
In order to merge following patch to drm-intel-gt-next:
https://patchwork.freedesktop.org/patch/530942/?series=114925&rev=6
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index 4a122925c3ae..92c18bfb98b3 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -532,6 +532,9 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, if (dmub->hw_funcs.reset) dmub->hw_funcs.reset(dmub); + /* reset the cache of the last wptr as well now that hw is reset */ + dmub->inbox1_last_wptr = 0; + cw0.offset.quad_part = inst_fb->gpu_addr; cw0.region.base = DMUB_CW0_BASE; cw0.region.top = cw0.region.base + inst_fb->size - 1; @@ -649,6 +652,15 @@ enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) if (dmub->hw_funcs.reset) dmub->hw_funcs.reset(dmub); + /* mailboxes have been reset in hw, so reset the sw state as well */ + dmub->inbox1_last_wptr = 0; + dmub->inbox1_rb.wrpt = 0; + dmub->inbox1_rb.rptr = 0; + dmub->outbox0_rb.wrpt = 0; + dmub->outbox0_rb.rptr = 0; + dmub->outbox1_rb.wrpt = 0; + dmub->outbox1_rb.rptr = 0; + dmub->hw_init = false; return DMUB_STATUS_OK; |