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| author | Alvin Lee <alvin.lee2@amd.com> | 2023-08-10 11:50:52 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-08-30 14:59:14 -0400 |
| commit | 0b9dc439f4046ef9e43f54989f6c3ff6cddc6d1b (patch) | |
| tree | 0097a2d4ffa00fc469b78031cb49856593ac84c3 /drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | |
| parent | ec4247823bbc88a7ee81fec579d1b4408bba686d (diff) | |
| download | linux-0b9dc439f4046ef9e43f54989f6c3ff6cddc6d1b.tar.gz linux-0b9dc439f4046ef9e43f54989f6c3ff6cddc6d1b.tar.bz2 linux-0b9dc439f4046ef9e43f54989f6c3ff6cddc6d1b.zip | |
drm/amd/display: Write flip addr to scratch reg for subvp
[Description]
SubVP needs to "calculate" the earliest in use META address
by using the current primary / meta addresses, but this leads
to a race condition where FW and driver can read/write the
address at the same time and intermittently produce inconsistent
address offsets. To mitigate this issue without locking (too slow),
save each surface flip addr into scratch registers and use this
to keep track of the earliest in use META addres.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 02ff99f7bec2..ca064e70c22f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -134,6 +134,12 @@ struct set_ocsc_default_params { enum mpc_output_csc_mode ocsc_mode; }; +struct subvp_save_surf_addr { + struct dc_dmub_srv *dc_dmub_srv; + const struct dc_plane_address *addr; + uint8_t subvp_index; +}; + union block_sequence_params { struct update_plane_addr_params update_plane_addr_params; struct subvp_pipe_control_lock_fast_params subvp_pipe_control_lock_fast_params; @@ -151,6 +157,7 @@ union block_sequence_params { struct power_on_mpc_mem_pwr_params power_on_mpc_mem_pwr_params; struct set_output_csc_params set_output_csc_params; struct set_ocsc_default_params set_ocsc_default_params; + struct subvp_save_surf_addr subvp_save_surf_addr; }; enum block_sequence_func { @@ -170,6 +177,7 @@ enum block_sequence_func { MPC_POWER_ON_MPC_MEM_PWR, MPC_SET_OUTPUT_CSC, MPC_SET_OCSC_DEFAULT, + DMUB_SUBVP_SAVE_SURF_ADDR, }; struct block_sequence { @@ -471,4 +479,6 @@ void hwss_set_output_csc(union block_sequence_params *params); void hwss_set_ocsc_default(union block_sequence_params *params); +void hwss_subvp_save_surf_addr(union block_sequence_params *params); + #endif /* __DC_HW_SEQUENCER_H__ */ |