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| author | Harry Wentland <harry.wentland@amd.com> | 2019-02-25 13:26:34 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:07 -0500 |
| commit | 97bda0322b8a91aa8d534763e709571b2334e585 (patch) | |
| tree | 9e572c249b54a91c58a771d5eeef5ffc51cfe587 /drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | |
| parent | b4f199c7b00c87183f10c0a8f635f26ba2ede3eb (diff) | |
| download | linux-97bda0322b8a91aa8d534763e709571b2334e585.tar.gz linux-97bda0322b8a91aa8d534763e709571b2334e585.tar.bz2 linux-97bda0322b8a91aa8d534763e709571b2334e585.zip | |
drm/amd/display: Add DSC support for Navi (v2)
Add support for DCN2 DSC (Display Stream Compression)
HW Blocks:
+--------++------+ +----------+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+--------++------+ +----------+
| ^
v |
+--------+ +--------+
| DPP | | DWB |
+--------+ +--------+
|
v ^
+--------+ |
| MPC | |
+--------+ |
| |
v |
+-------+ +-------+ |
| OPP | <--> | DSC | |
+-------+ +-------+ |
| |
v |
+--------+ /
| OPTC | --------------
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
v2: rebase (Alex)
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index f84ce4de53ca..d8418c27fd35 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -109,8 +109,22 @@ struct stream_encoder { enum engine_id id; }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +struct enc_state { + uint32_t dsc_mode; // DISABLED 0; 1 or 2 indicate enabled state. + uint32_t dsc_slice_width; + uint32_t sec_gsp7_line_num; + uint32_t vbid6_line_reference; + uint32_t vbid6_line_num; + uint32_t sec_gsp7_enable; + uint32_t sec_stream_enable; +}; +#endif struct stream_encoder_funcs { + #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void (*enc_read_state)(struct stream_encoder *enc, struct enc_state *s); + #endif void (*dp_set_stream_attribute)( struct stream_encoder *enc, struct dc_crtc_timing *crtc_timing, @@ -198,6 +212,14 @@ struct stream_encoder_funcs { int tg_inst); #if defined(CONFIG_DRM_AMD_DC_DCN2_0) +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + void (*dp_set_dsc_config)( + struct stream_encoder *enc, + enum optc_dsc_mode dsc_mode, + uint32_t dsc_bytes_per_pixel, + uint32_t dsc_slice_width, + uint8_t *dsc_packed_pps); +#endif void (*set_dynamic_metadata)(struct stream_encoder *enc, bool enable, |