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| author | Daniel Miess <daniel.miess@amd.com> | 2023-11-03 13:52:53 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-04-09 21:59:07 -0400 |
| commit | c9c703952600845a3a59ef9670e5b2d037457c81 (patch) | |
| tree | 8c504c7e91656861d01a419d3e4c8d4ff89b1b37 /drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | |
| parent | 62297b71a02d73e761470f7907ec1ce63bb3615c (diff) | |
| download | linux-c9c703952600845a3a59ef9670e5b2d037457c81.tar.gz linux-c9c703952600845a3a59ef9670e5b2d037457c81.tar.bz2 linux-c9c703952600845a3a59ef9670e5b2d037457c81.zip | |
drm/amd/display: Toggle additional RCO options in DCN35
[Why]
With root clock optimization now enabled for DCN35 there
are still RCO registers still not being toggled
[How]
Add in logic to toggle RCO registers for DPPCLK,
DPSTREAMCLK and DSCCLK
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 722eff84ccfd..d4c7885fc916 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -106,6 +106,10 @@ struct dccg_funcs { void (*otg_drop_pixel)(struct dccg *dccg, uint32_t otg_inst); void (*dccg_init)(struct dccg *dccg); + void (*set_dpstreamclk_root_clock_gating)( + struct dccg *dccg, + int dp_hpo_inst, + bool enable); void (*set_dpstreamclk)( struct dccg *dccg, |