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| author | Webb Chen <yi-lchen@amd.com> | 2024-02-27 10:01:25 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-04-30 09:49:45 -0400 |
| commit | 4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49 (patch) | |
| tree | a5bb0b06c29b553ddf26dd8e4f6687029fb03107 /drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | |
| parent | a8ac994cf0693a1ce59410995594e56124a1c79f (diff) | |
| download | linux-4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49.tar.gz linux-4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49.tar.bz2 linux-4d4d3ff16db2642ade8b2fd64cb1abd65bddcf49.zip | |
drm/amd/display: Keep VBios pixel rate div setting util next mode set
[why]
VBios & Driver may have differnet pixel rate div policy.
If the policy is not same and fast boot is enabled,
it would cause the pixel rate is too high
after driver only performs stream blank & unblank.
[how]
We would keep pixel rate div setting by VBios until next mode set.
Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Webb Chen <yi-lchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index d4c7885fc916..d6248a73c7c1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -176,6 +176,11 @@ struct dccg_funcs { enum pixel_rate_div k1, enum pixel_rate_div k2); + void (*get_pixel_rate_div)(struct dccg *dccg, + uint32_t otg_inst, + uint32_t *div_factor1, + uint32_t *div_factor2); + void (*set_valid_pixel_rate)( struct dccg *dccg, int ref_dtbclk_khz, |