diff options
| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2021-05-19 12:22:47 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-06-04 16:39:18 -0400 |
| commit | 74458c081fcfb0423877e630de2746daefdb16e4 (patch) | |
| tree | 362f25f759ef2dc1613f36e6b3ab16b06a446d5b /drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c | |
| parent | ba5a5371812e1f177414d30a9ce9691017cf30b6 (diff) | |
| download | linux-74458c081fcfb0423877e630de2746daefdb16e4.tar.gz linux-74458c081fcfb0423877e630de2746daefdb16e4.tar.bz2 linux-74458c081fcfb0423877e630de2746daefdb16e4.zip | |
drm/amd/display: Add DCN3.1 DML calculation support
DML (Display mode library) is used for calculating watermarks, bandwidth
and for validating display configurations.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c index 1f7b6ddf3020..9bb3b00e8be1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c @@ -34,6 +34,10 @@ #include "dcn30/display_mode_vba_30.h" #include "dcn30/display_rq_dlg_calc_30.h" #include "dml_logger.h" +#ifdef CONFIG_DRM_AMD_DC_DCN3_1 +#include "dcn31/display_mode_vba_31.h" +#include "dcn31/display_rq_dlg_calc_31.h" +#endif const struct dml_funcs dml20_funcs = { .validate = dml20_ModeSupportAndSystemConfigurationFull, @@ -62,6 +66,14 @@ const struct dml_funcs dml30_funcs = { .rq_dlg_get_dlg_reg = dml30_rq_dlg_get_dlg_reg, .rq_dlg_get_rq_reg = dml30_rq_dlg_get_rq_reg }; +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) +const struct dml_funcs dml31_funcs = { + .validate = dml31_ModeSupportAndSystemConfigurationFull, + .recalculate = dml31_recalculate, + .rq_dlg_get_dlg_reg = dml31_rq_dlg_get_dlg_reg, + .rq_dlg_get_rq_reg = dml31_rq_dlg_get_rq_reg +}; +#endif void dml_init_instance(struct display_mode_lib *lib, const struct _vcs_dpi_soc_bounding_box_st *soc_bb, @@ -84,7 +96,13 @@ void dml_init_instance(struct display_mode_lib *lib, case DML_PROJECT_DCN30: lib->funcs = dml30_funcs; break; +#if defined(CONFIG_DRM_AMD_DC_DCN3_1) + case DML_PROJECT_DCN31: + case DML_PROJECT_DCN31_FPGA: + lib->funcs = dml31_funcs; + break; +#endif default: break; } |