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| author | Alvin Lee <alvin.lee2@amd.com> | 2023-05-31 20:00:54 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-15 10:44:39 -0400 |
| commit | 196754951fc8187c64806d0807c467d6f435d0c5 (patch) | |
| tree | 9d667f9d46b9236135b5e3f9eb4352d84116bc71 /drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c | |
| parent | d62088ba314ecf098871874898ed760347d1fbd8 (diff) | |
| download | linux-196754951fc8187c64806d0807c467d6f435d0c5.tar.gz linux-196754951fc8187c64806d0807c467d6f435d0c5.tar.bz2 linux-196754951fc8187c64806d0807c467d6f435d0c5.zip | |
drm/amd/display: Block SubVP + DRR if the DRR is PSR capable
[Description]
PSR implementation in FW has inline polling which can poll for up
to 1ms. This will interfere with SubVP because SubVP is timing
sensitive and can't tolerate up to 1ms worth of delay before
handling vertical or VLINE interrupts. Therefore block SubVP + DRR
cases if DRR is PSR capable
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Reviewed-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c')
0 files changed, 0 insertions, 0 deletions