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| author | Webb Chen <yi-lchen@amd.com> | 2024-02-27 10:01:25 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-04-30 09:54:36 -0400 |
| commit | 532a0d2ad2920bc18e73566a112feccfd55ff4de (patch) | |
| tree | a3518ef0da843f7e8f9c7f27119c84087e2d75b4 /drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | |
| parent | f2303026a5b6327247ba61152d00199b2d1be294 (diff) | |
| download | linux-532a0d2ad2920bc18e73566a112feccfd55ff4de.tar.gz linux-532a0d2ad2920bc18e73566a112feccfd55ff4de.tar.bz2 linux-532a0d2ad2920bc18e73566a112feccfd55ff4de.zip | |
drm/amd/display: Revert "dc: Keep VBios pixel rate div setting util next mode set"
This reverts commit 4d4d3ff16db2 ("drm/amd/display: Keep VBios pixel rate div
setting util next mode set") which causes issue.
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Webb Chen <yi-lchen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c index 21a6ca5ca192..56385cede113 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c @@ -58,8 +58,8 @@ static void dccg32_trigger_dio_fifo_resync( static void dccg32_get_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, - uint32_t *k1, - uint32_t *k2) + enum pixel_rate_div *k1, + enum pixel_rate_div *k2) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); uint32_t val_k1 = PIXEL_RATE_DIV_NA, val_k2 = PIXEL_RATE_DIV_NA; @@ -93,8 +93,8 @@ static void dccg32_get_pixel_rate_div( return; } - *k1 = val_k1; - *k2 = val_k2; + *k1 = (enum pixel_rate_div)val_k1; + *k2 = (enum pixel_rate_div)val_k2; } static void dccg32_set_pixel_rate_div( @@ -104,8 +104,7 @@ static void dccg32_set_pixel_rate_div( enum pixel_rate_div k2) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - uint32_t cur_k1 = PIXEL_RATE_DIV_NA; - uint32_t cur_k2 = PIXEL_RATE_DIV_NA; + enum pixel_rate_div cur_k1 = PIXEL_RATE_DIV_NA, cur_k2 = PIXEL_RATE_DIV_NA; // Don't program 0xF into the register field. Not valid since // K1 / K2 field is only 1 / 2 bits wide @@ -344,7 +343,6 @@ static const struct dccg_funcs dccg32_funcs = { .otg_add_pixel = dccg32_otg_add_pixel, .otg_drop_pixel = dccg32_otg_drop_pixel, .set_pixel_rate_div = dccg32_set_pixel_rate_div, - .get_pixel_rate_div = dccg32_get_pixel_rate_div, .trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync, .set_dtbclk_p_src = dccg32_set_dtbclk_p_src, }; |