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| author | Eric Bernstein <eric.bernstein@amd.com> | 2022-04-01 13:49:45 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-07-05 16:11:00 -0400 |
| commit | 64a30aaf0b0d9dcd52af526652937c1350a948dc (patch) | |
| tree | 5215b5d6627953da73ad8c6775800f3422680fdd /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | |
| parent | 90f33674a0756a6f0907b8f6350cec3f7be4032c (diff) | |
| download | linux-64a30aaf0b0d9dcd52af526652937c1350a948dc.tar.gz linux-64a30aaf0b0d9dcd52af526652937c1350a948dc.tar.bz2 linux-64a30aaf0b0d9dcd52af526652937c1350a948dc.zip | |
drm/amd/display: Add function to set pixels per cycle
Add function to set pixels per cycle in DIG stream encoder
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index f8d22ba6a6e4..aa4f41745be4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -577,6 +577,7 @@ struct dcn10_stream_enc_registers { #define SE_REG_FIELD_LIST_DCN3_2(type) \ type DIG_FIFO_OUTPUT_PIXEL_MODE;\ + type DP_PIXEL_PER_CYCLE_PROCESSING_MODE;\ type DIG_SYMCLK_FE_ON;\ type DIG_FIFO_READ_START_LEVEL;\ type DIG_FIFO_ENABLE;\ |