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| author | Charlene Liu <charlene.liu@amd.com> | 2018-01-18 19:09:06 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-02-19 14:19:34 -0500 |
| commit | 5180d4a4766d7df4b3ffae919f867ce9598d8942 (patch) | |
| tree | 22104dd26c169a46fab2b511fad280af3966104d /drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | |
| parent | 60eb6d98ec72382478a854262dee50426772214c (diff) | |
| download | linux-5180d4a4766d7df4b3ffae919f867ce9598d8942.tar.gz linux-5180d4a4766d7df4b3ffae919f867ce9598d8942.tar.bz2 linux-5180d4a4766d7df4b3ffae919f867ce9598d8942.zip | |
drm/amd/display: add eDP 1.2+ polling for T7
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 83bae207371d..8146b9079d51 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -920,6 +920,7 @@ static void dce110_stream_encoder_dp_blank( { struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); uint32_t retries = 0; + uint32_t reg1 = 0; uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; /* Note: For CZ, we are changing driver default to disable @@ -928,7 +929,10 @@ static void dce110_stream_encoder_dp_blank( * handful of panels that cannot handle disable stream at * HBLANK and will result in a white line flash across the * screen on stream disable. */ - + REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); + if ((reg1 & 0x1) == 0) + /*stream not enabled*/ + return; /* Specify the video stream disable point * (2 = start of the next vertical blank) */ REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); |